Mesa (staging/23.3): radv: fix compute shader invocations query on compute queue on GFX6

[GitLab Mirror]

Module: Mesa
Branch: staging/23.3
Commit: 18397e51adc40a814e945181196c4b5d94f5bb51
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=18397e51adc40a814e945181196c4b5d94f5bb51

Author: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Date:   Mon Oct 30 12:50:56 2023 +0100

radv: fix compute shader invocations query on compute queue on GFX6

Looks like GFX6 always writes the number of compute shader invocations
at offset 0 when used on compute queue.

This fixes dEQP-VK.query_pool.statistics_query.*_cq on GFX6.

Fixes: a9945216ba2 ("radv: fix COMPUTE_SHADER_INVOCATIONS query on compute 
queue")
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25957>
(cherry picked from commit 9a0a77cb53d0d31c7a090d06ac905d69e9c1131c)

---

 .pick_status.json           | 2 +-
 src/amd/vulkan/radv_query.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index a81f38714e5..757fb016ad9 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -74,7 +74,7 @@
         "description": "radv: fix compute shader invocations query on compute 
queue on GFX6",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "a9945216ba223d57ade453d5f855edd93dd3b200",
         "notes": null
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 7e43604c8bc..02339b508be 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -1755,7 +1755,7 @@ emit_begin_query(struct radv_cmd_buffer *cmd_buffer, 
struct radv_query_pool *poo
 
       radv_update_hw_pipelinestat(cmd_buffer);
 
-      if (cmd_buffer->qf == RADV_QUEUE_COMPUTE) {
+      if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
          uint32_t cs_invoc_offset =
             
radv_get_pipelinestat_query_offset(VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT);
          va += cs_invoc_offset;
@@ -1916,7 +1916,7 @@ emit_end_query(struct radv_cmd_buffer *cmd_buffer, struct 
radv_query_pool *pool,
 
       va += pipelinestat_block_size;
 
-      if (cmd_buffer->qf == RADV_QUEUE_COMPUTE) {
+      if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
          uint32_t cs_invoc_offset =
             
radv_get_pipelinestat_query_offset(VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT);
          va += cs_invoc_offset;