Module: Mesa Branch: main Commit: 6cd78281f646d51e03ecca0473ef595b671b673b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6cd78281f646d51e03ecca0473ef595b671b673b
Author: Georg Lehmann <dadschoo...@gmail.com> Date: Sat Oct 28 12:53:00 2023 +0200 aco: deduplicate Format definition Reviewed-by: Daniel Schürmann <dan...@schuermann.dev Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25943> --- src/amd/compiler/aco_ir.h | 55 +--------------------------- src/amd/compiler/aco_opcodes.py | 75 ++++++++++++++++++++++++--------------- src/amd/compiler/aco_opcodes_h.py | 10 ++++-- src/amd/compiler/aco_validate.cpp | 2 +- 4 files changed, 56 insertions(+), 86 deletions(-) diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h index d70533688de..3d3a727b028 100644 --- a/src/amd/compiler/aco_ir.h +++ b/src/amd/compiler/aco_ir.h @@ -59,59 +59,6 @@ enum { DEBUG_NO_VALIDATE_IR = 0x400, }; -/** - * Representation of the instruction's microcode encoding format - * Note: Some Vector ALU Formats can be combined, such that: - * - VOP2* | VOP3 represents a VOP2 instruction in VOP3 encoding - * - VOP2* | DPP represents a VOP2 instruction with data parallel primitive. - * - VOP2* | SDWA represents a VOP2 instruction with sub-dword addressing. - * - * (*) The same is applicable for VOP1 and VOPC instructions. - */ -enum class Format : uint16_t { - /* Pseudo Instruction Format */ - PSEUDO = 0, - /* Scalar ALU & Control Formats */ - SOP1 = 1, - SOP2 = 2, - SOPK = 3, - SOPP = 4, - SOPC = 5, - /* Scalar Memory Format */ - SMEM = 6, - /* LDS/GDS Format */ - DS = 8, - LDSDIR = 9, - /* Vector Memory Buffer Formats */ - MTBUF = 10, - MUBUF = 11, - /* Vector Memory Image Format */ - MIMG = 12, - /* Export Format */ - EXP = 13, - /* Flat Formats */ - FLAT = 14, - GLOBAL = 15, - SCRATCH = 16, - - PSEUDO_BRANCH = 17, - PSEUDO_BARRIER = 18, - PSEUDO_REDUCTION = 19, - - /* Vector ALU Formats */ - VINTERP_INREG = 21, - VOP3P = 1 << 7, - VOP1 = 1 << 8, - VOP2 = 1 << 9, - VOPC = 1 << 10, - VOP3 = 1 << 11, - /* Vector Parameter Interpolation Format */ - VINTRP = 1 << 12, - DPP16 = 1 << 13, - SDWA = 1 << 14, - DPP8 = 1 << 15, -}; - enum storage_class : uint8_t { storage_none = 0x0, /* no synchronization and can be reordered around aliasing stores */ storage_buffer = 0x1, /* SSBOs and global memory */ @@ -1278,7 +1225,7 @@ struct Instruction { assert(isVINTRP()); return *(VINTRP_instruction*)this; } - constexpr bool isVINTRP() const noexcept { return (uint16_t)format & (uint16_t)Format::VINTRP; } + constexpr bool isVINTRP() const noexcept { return format == Format::VINTRP; } DPP16_instruction& dpp16() noexcept { assert(isDPP16()); diff --git a/src/amd/compiler/aco_opcodes.py b/src/amd/compiler/aco_opcodes.py index 2fe9981073e..61479cbaf0c 100644 --- a/src/amd/compiler/aco_opcodes.py +++ b/src/amd/compiler/aco_opcodes.py @@ -25,7 +25,7 @@ # NOTE: this must be kept in sync with aco_op_info import sys -from enum import Enum +from enum import Enum, IntEnum, auto class InstrClass(Enum): Valu32 = "valu32" @@ -50,36 +50,53 @@ class InstrClass(Enum): Waitcnt = "waitcnt" Other = "other" -class Format(Enum): +# Representation of the instruction's microcode encoding format +# Note: Some Vector ALU Formats can be combined, such that: +# - VOP2* | VOP3 represents a VOP2 instruction in VOP3 encoding +# - VOP2* | DPP represents a VOP2 instruction with data parallel primitive. +# - VOP2* | SDWA represents a VOP2 instruction with sub-dword addressing. +# +# (*) The same is applicable for VOP1 and VOPC instructions. +class Format(IntEnum): + # Pseudo Instruction Formats PSEUDO = 0 - SOP1 = 1 - SOP2 = 2 - SOPK = 3 - SOPP = 4 - SOPC = 5 - SMEM = 6 - DS = 8 - LDSDIR = 9 - MTBUF = 10 - MUBUF = 11 - MIMG = 12 - EXP = 13 - FLAT = 14 - GLOBAL = 15 - SCRATCH = 16 - PSEUDO_BRANCH = 17 - PSEUDO_BARRIER = 18 - PSEUDO_REDUCTION = 19 - VINTERP_INREG = 21 - VOP3P = 1 << 7 - VOP1 = 1 << 8 - VOP2 = 1 << 9 - VOPC = 1 << 10 - VOP3 = 1 << 11 - VINTRP = 1 << 12 + PSEUDO_BRANCH = auto() + PSEUDO_BARRIER = auto() + PSEUDO_REDUCTION = auto() + # Scalar ALU & Control Formats + SOP1 = auto() + SOP2 = auto() + SOPK = auto() + SOPP = auto() + SOPC = auto() + # Scalar Memory Format + SMEM = auto() + # LDS/GDS Format + DS = auto() + LDSDIR = auto() + # Vector Memory Buffer Formats + MTBUF = auto() + MUBUF = auto() + # Vector Memory Image Format + MIMG = auto() + # Export Format + EXP = auto() + # Flat Formats + FLAT = auto() + GLOBAL = auto() + SCRATCH = auto() + # Vector Parameter Interpolation Formats + VINTRP = auto() + # Vector ALU Formats + VINTERP_INREG = auto() + VOP1 = 1 << 7 + VOP2 = 1 << 8 + VOPC = 1 << 9 + VOP3 = 1 << 10 + VOP3P = 1 << 11 + SDWA = 1 << 12 DPP16 = 1 << 13 - SDWA = 1 << 14 - DPP8 = 1 << 15 + DPP8 = 1 << 14 def get_builder_fields(self): if self == Format.SOPK: diff --git a/src/amd/compiler/aco_opcodes_h.py b/src/amd/compiler/aco_opcodes_h.py index b9dd26e3ef1..40993dab65e 100644 --- a/src/amd/compiler/aco_opcodes_h.py +++ b/src/amd/compiler/aco_opcodes_h.py @@ -32,6 +32,12 @@ template = """\ namespace aco { +enum class Format : uint16_t { +% for e in Format: + ${e.name} = ${hex(e.value)}, +% endfor +}; + enum class instr_class : uint8_t { % for name in InstrClass: ${name.value}, @@ -52,7 +58,7 @@ enum class aco_opcode : uint16_t { } #endif /* _ACO_OPCODES_ */""" -from aco_opcodes import opcodes, InstrClass +from aco_opcodes import opcodes, InstrClass, Format from mako.template import Template -print(Template(template).render(opcodes=opcodes, InstrClass=InstrClass)) +print(Template(template).render(opcodes=opcodes, InstrClass=InstrClass, Format=Format)) diff --git a/src/amd/compiler/aco_validate.cpp b/src/amd/compiler/aco_validate.cpp index f344b48d43f..fd70b343e9c 100644 --- a/src/amd/compiler/aco_validate.cpp +++ b/src/amd/compiler/aco_validate.cpp @@ -116,7 +116,7 @@ validate_ir(Program* program) base_format = Format::VOP2; else if ((uint32_t)base_format & (uint32_t)Format::VOPC) base_format = Format::VOPC; - else if ((uint32_t)base_format & (uint32_t)Format::VINTRP) { + else if (base_format == Format::VINTRP) { if (instr->opcode == aco_opcode::v_interp_p1ll_f16 || instr->opcode == aco_opcode::v_interp_p1lv_f16 || instr->opcode == aco_opcode::v_interp_p2_legacy_f16 ||
