Module: Mesa Branch: main Commit: 34b68c9017718409fd46f720c8fe6f3a9758f517 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=34b68c9017718409fd46f720c8fe6f3a9758f517
Author: Marek Olšák <marek.ol...@amd.com> Date: Tue Oct 24 07:57:45 2023 -0400 radeonsi: don't check DCC compatibility on chips where it's no-op Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-pra...@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095> --- src/gallium/drivers/radeonsi/si_state.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index aff069c7d1c..d40d87ee62c 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2869,21 +2869,23 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, si_update_fb_dirtiness_after_rendering(sctx); /* Disable DCC if the formats are incompatible. */ - for (i = 0; i < state->nr_cbufs; i++) { - if (!state->cbufs[i]) - continue; + if (sctx->gfx_level >= GFX8 && sctx->gfx_level < GFX11) { + for (i = 0; i < state->nr_cbufs; i++) { + if (!state->cbufs[i]) + continue; - surf = (struct si_surface *)state->cbufs[i]; - tex = (struct si_texture *)surf->base.texture; + surf = (struct si_surface *)state->cbufs[i]; + tex = (struct si_texture *)surf->base.texture; - if (!surf->dcc_incompatible) - continue; + if (!surf->dcc_incompatible) + continue; - if (vi_dcc_enabled(tex, surf->base.u.tex.level)) - if (!si_texture_disable_dcc(sctx, tex)) - si_decompress_dcc(sctx, tex); + if (vi_dcc_enabled(tex, surf->base.u.tex.level)) + if (!si_texture_disable_dcc(sctx, tex)) + si_decompress_dcc(sctx, tex); - surf->dcc_incompatible = false; + surf->dcc_incompatible = false; + } } /* Only flush TC when changing the framebuffer state, because
