Module: Mesa Branch: main Commit: 6a31c7a8416ea2c0d0d8d865073fa796bb37a5d5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a31c7a8416ea2c0d0d8d865073fa796bb37a5d5
Author: Marek Olšák <marek.ol...@amd.com> Date: Wed Oct 25 04:30:41 2023 -0400 radeonsi: move SPI_SHADER_IDX_FORMAT into the preamble (it's immutable) Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-pra...@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095> --- src/gallium/drivers/radeonsi/si_gfx_cs.c | 1 - src/gallium/drivers/radeonsi/si_shader.h | 1 - src/gallium/drivers/radeonsi/si_state.c | 2 ++ src/gallium/drivers/radeonsi/si_state.h | 3 +-- src/gallium/drivers/radeonsi/si_state_shaders.cpp | 8 +++----- 5 files changed, 6 insertions(+), 9 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index b22f4d24951..65e661ef44d 100644 --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c @@ -215,7 +215,6 @@ void si_set_tracked_regs_to_clear_state(struct si_context *ctx) ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ] = 0x3f800000; ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ] = 0x3f800000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_SHADER_IDX_FORMAT] = 0; ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_SHADER_POS_FORMAT] = 0; ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_SHADER_Z_FORMAT] = 0; diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h index 5d5816f619b..95038c70dba 100644 --- a/src/gallium/drivers/radeonsi/si_shader.h +++ b/src/gallium/drivers/radeonsi/si_shader.h @@ -940,7 +940,6 @@ struct si_shader { unsigned vgt_gs_instance_cnt; unsigned esgs_vertex_stride; unsigned spi_vs_out_config; - unsigned spi_shader_idx_format; unsigned spi_shader_pos_format; unsigned pa_cl_vte_cntl; unsigned vgt_gs_max_vert_out; /* for API GS */ diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 34bf648a0ea..909500c82ea 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -6022,6 +6022,8 @@ static void gfx10_init_gfx_preamble_state(struct si_context *sctx) S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_GFX10) | S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_GFX10)) | S_028410_DCC_RD_POLICY(meta_read_policy)); + si_pm4_set_reg(pm4, R_028708_SPI_SHADER_IDX_FORMAT, + S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP)); if (sctx->gfx_level >= GFX10_3) si_pm4_set_reg(pm4, R_028750_SX_PS_DOWNCONVERT_CONTROL, 0xff); diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index 542db0faa05..0d094b4ce95 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -250,8 +250,7 @@ enum si_tracked_context_reg SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ, SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ, - /* 2 consecutive registers */ - SI_TRACKED_SPI_SHADER_IDX_FORMAT, + /* Non-consecutive register */ SI_TRACKED_SPI_SHADER_POS_FORMAT, /* 2 consecutive registers */ diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp index 07594052efb..9137c7a2503 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp +++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp @@ -1199,10 +1199,9 @@ static void gfx10_emit_shader_ngg(struct si_context *sctx, unsigned index) shader->ngg.vgt_gs_instance_cnt); radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG, shader->ngg.spi_vs_out_config); - radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT, - SI_TRACKED_SPI_SHADER_IDX_FORMAT, - shader->ngg.spi_shader_idx_format, - shader->ngg.spi_shader_pos_format); + radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT, + SI_TRACKED_SPI_SHADER_POS_FORMAT, + shader->ngg.spi_shader_pos_format); radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL, shader->ngg.pa_cl_vte_cntl); radeon_end_update_context_roll(sctx); @@ -1372,7 +1371,6 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader S_00B22C_LDS_SIZE(shader->config.lds_size)); /* Set register values emitted conditionally in gfx10_emit_shader_ngg_*. */ - shader->ngg.spi_shader_idx_format = S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP); shader->ngg.spi_shader_pos_format = S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) | S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
