Module: Mesa Branch: main Commit: d2125dac859607ceef1586730d7b9797d76b7cd7 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2125dac859607ceef1586730d7b9797d76b7cd7
Author: Caio Oliveira <caio.olive...@intel.com> Date: Tue Oct 31 23:37:20 2023 -0700 intel/compiler: Take more precise params in brw_nir_optimize() Reviewed-by: Sagar Ghuge <sagar.gh...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25986> --- src/intel/compiler/brw_nir.c | 40 ++++++++++++++++++++++------------------ src/intel/compiler/brw_nir.h | 4 ++-- src/intel/compiler/brw_nir_rt.c | 3 ++- 3 files changed, 26 insertions(+), 21 deletions(-) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 72956db33ca..413a0d3cce2 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -602,14 +602,14 @@ brw_nir_lower_fs_outputs(nir_shader *nir) }) void -brw_nir_optimize(nir_shader *nir, const struct brw_compiler *compiler) +brw_nir_optimize(nir_shader *nir, bool is_scalar, + const struct intel_device_info *devinfo) { bool progress; unsigned lower_flrp = (nir->options->lower_flrp16 ? 16 : 0) | (nir->options->lower_flrp32 ? 32 : 0) | (nir->options->lower_flrp64 ? 64 : 0); - const bool is_scalar = compiler->scalar_stage[nir->info.stage]; do { progress = false; @@ -680,7 +680,7 @@ brw_nir_optimize(nir_shader *nir, const struct brw_compiler *compiler) nir->info.stage == MESA_SHADER_TESS_EVAL); OPT(nir_opt_peephole_select, 0, !is_vec4_tessellation, false); OPT(nir_opt_peephole_select, 8, !is_vec4_tessellation, - compiler->devinfo->ver >= 6); + devinfo->ver >= 6); OPT(nir_opt_intrinsics); OPT(nir_opt_idiv_const, 32); @@ -689,7 +689,7 @@ brw_nir_optimize(nir_shader *nir, const struct brw_compiler *compiler) /* BFI2 did not exist until Gfx7, so there's no point in trying to * optimize an instruction that should not get generated. */ - if (compiler->devinfo->ver >= 7) + if (devinfo->ver >= 7) OPT(nir_opt_reassociate_bfi); OPT(nir_lower_constant_convert_alu_types); @@ -961,7 +961,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir, OPT(nir_split_var_copies); OPT(nir_split_struct_vars, nir_var_function_temp); - brw_nir_optimize(nir, compiler); + brw_nir_optimize(nir, is_scalar, devinfo); OPT(nir_lower_doubles, opts->softfp64, nir->options->lower_doubles_options); if (OPT(nir_lower_int64_float_conversions)) { @@ -1044,7 +1044,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir, OPT(brw_nir_clamp_per_vertex_loads); /* Get rid of split copies */ - brw_nir_optimize(nir, compiler); + brw_nir_optimize(nir, is_scalar, devinfo); } static bool @@ -1162,6 +1162,8 @@ void brw_nir_link_shaders(const struct brw_compiler *compiler, nir_shader *producer, nir_shader *consumer) { + const struct intel_device_info *devinfo = compiler->devinfo; + if (producer->info.stage == MESA_SHADER_MESH && consumer->info.stage == MESA_SHADER_FRAGMENT) { uint64_t fs_inputs = 0, ms_outputs = 0; @@ -1204,12 +1206,12 @@ brw_nir_link_shaders(const struct brw_compiler *compiler, if (p_is_scalar && c_is_scalar) { NIR_PASS(_, producer, nir_lower_io_to_scalar_early, nir_var_shader_out); NIR_PASS(_, consumer, nir_lower_io_to_scalar_early, nir_var_shader_in); - brw_nir_optimize(producer, compiler); - brw_nir_optimize(consumer, compiler); + brw_nir_optimize(producer, p_is_scalar, devinfo); + brw_nir_optimize(consumer, c_is_scalar, devinfo); } if (nir_link_opt_varyings(producer, consumer)) - brw_nir_optimize(consumer, compiler); + brw_nir_optimize(consumer, c_is_scalar, devinfo); NIR_PASS(_, producer, nir_remove_dead_variables, nir_var_shader_out, NULL); NIR_PASS(_, consumer, nir_remove_dead_variables, nir_var_shader_in, NULL); @@ -1238,8 +1240,8 @@ brw_nir_link_shaders(const struct brw_compiler *compiler, brw_nir_no_indirect_mask(compiler, consumer->info.stage), UINT32_MAX); - brw_nir_optimize(producer, compiler); - brw_nir_optimize(consumer, compiler); + brw_nir_optimize(producer, p_is_scalar, devinfo); + brw_nir_optimize(consumer, c_is_scalar, devinfo); if (producer->info.stage == MESA_SHADER_MESH && consumer->info.stage == MESA_SHADER_FRAGMENT) { @@ -1587,20 +1589,20 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, if (gl_shader_stage_can_set_fragment_shading_rate(nir->info.stage)) NIR_PASS(_, nir, brw_nir_lower_shading_rate_output); - brw_nir_optimize(nir, compiler); + brw_nir_optimize(nir, is_scalar, devinfo); if (is_scalar && nir_shader_has_local_variables(nir)) { OPT(nir_lower_vars_to_explicit_types, nir_var_function_temp, glsl_get_natural_size_align_bytes); OPT(nir_lower_explicit_io, nir_var_function_temp, nir_address_format_32bit_offset); - brw_nir_optimize(nir, compiler); + brw_nir_optimize(nir, is_scalar, devinfo); } brw_vectorize_lower_mem_access(nir, compiler, robust_flags); if (OPT(nir_lower_int64)) - brw_nir_optimize(nir, compiler); + brw_nir_optimize(nir, is_scalar, devinfo); if (devinfo->ver >= 6) { /* Try and fuse multiply-adds, if successful, run shrink_vectors to @@ -1660,7 +1662,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, if (OPT(brw_nir_lower_conversions)) { if (OPT(nir_lower_int64)) { - brw_nir_optimize(nir, compiler); + brw_nir_optimize(nir, is_scalar, devinfo); } } @@ -1705,7 +1707,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, OPT(nir_lower_subgroups, &subgroups_options); if (OPT(nir_lower_int64)) - brw_nir_optimize(nir, compiler); + brw_nir_optimize(nir, is_scalar, devinfo); } /* Do this only after the last opt_gcm. GCM will undo this lowering. */ @@ -1884,8 +1886,10 @@ brw_nir_apply_key(nir_shader *nir, if (key->limit_trig_input_range) OPT(brw_nir_limit_trig_input_range_workaround); - if (progress) - brw_nir_optimize(nir, compiler); + if (progress) { + const bool is_scalar = compiler->scalar_stage[nir->info.stage]; + brw_nir_optimize(nir, is_scalar, compiler->devinfo); + } } enum brw_conditional_mod diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/brw_nir.h index 0b441b41ce2..fc365cc0f0a 100644 --- a/src/intel/compiler/brw_nir.h +++ b/src/intel/compiler/brw_nir.h @@ -267,8 +267,8 @@ bool brw_nir_lower_patch_vertices_in(nir_shader *shader, unsigned input_vertices bool brw_nir_blockify_uniform_loads(nir_shader *shader, const struct intel_device_info *devinfo); -void brw_nir_optimize(nir_shader *nir, - const struct brw_compiler *compiler); +void brw_nir_optimize(nir_shader *nir, bool is_scalar, + const struct intel_device_info *devinfo); nir_shader *brw_nir_create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compiler, diff --git a/src/intel/compiler/brw_nir_rt.c b/src/intel/compiler/brw_nir_rt.c index 6956e2d3583..ac9d76ac43d 100644 --- a/src/intel/compiler/brw_nir_rt.c +++ b/src/intel/compiler/brw_nir_rt.c @@ -527,7 +527,8 @@ brw_nir_create_raygen_trampoline(const struct brw_compiler *compiler, NIR_PASS_V(nir, brw_nir_lower_cs_intrinsics); - brw_nir_optimize(nir, compiler); + const bool is_scalar = true; + brw_nir_optimize(nir, is_scalar, devinfo); return nir; }
