Module: Mesa Branch: main Commit: 5fb6760f11089c9cbcd1ffa76d34e807bbb1d613 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5fb6760f11089c9cbcd1ffa76d34e807bbb1d613
Author: Francisco Jerez <curroje...@riseup.net> Date: Sat Feb 19 01:41:55 2022 -0800 intel/fs/xe2+: Teach SWSB pass about the behavior of double precision instructions. Xe2 hardware has a "long" EU pipeline specifically for FP64 instructions, so these are handled as in-order instructions which require RegDist synchronization. 64-bit integer instructions are now handled by the normal integer pipeline, so the existing special-casing inherited from ATS needs to be disabled. Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25514> --- src/intel/compiler/brw_fs_scoreboard.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs_scoreboard.cpp b/src/intel/compiler/brw_fs_scoreboard.cpp index c287fd62a5c..6e2ad22ee13 100644 --- a/src/intel/compiler/brw_fs_scoreboard.cpp +++ b/src/intel/compiler/brw_fs_scoreboard.cpp @@ -135,8 +135,13 @@ namespace { return TGL_PIPE_INT; else if (inst->opcode == FS_OPCODE_PACK_HALF_2x16_SPLIT) return TGL_PIPE_FLOAT; - else if (type_sz(inst->dst.type) >= 8 || type_sz(t) >= 8 || - is_dword_multiply) { + else if (devinfo->ver >= 20 && type_sz(inst->dst.type) >= 8 && + brw_reg_type_is_floating_point(inst->dst.type)) { + assert(devinfo->has_64bit_float); + return TGL_PIPE_LONG; + } else if (devinfo->ver < 20 && + (type_sz(inst->dst.type) >= 8 || type_sz(t) >= 8 || + is_dword_multiply)) { assert(devinfo->has_64bit_float || devinfo->has_64bit_int || devinfo->has_integer_dword_mul); return TGL_PIPE_LONG;
