Module: Mesa
Branch: main
Commit: ff3814abdd791c2ff7ab0dd0cbb4dbaa513208eb
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff3814abdd791c2ff7ab0dd0cbb4dbaa513208eb

Author: Francisco Jerez <curroje...@riseup.net>
Date:   Tue Aug  9 15:30:02 2022 -0700

intel/fs/xe2+: Handle extended math instructions as in-order in SWSB pass.

Extended math instructions are now synchronized as in-order
instructions like other ALU operations, which is more efficient than
the out-of-order tracking we had to do in previous generations, and
avoids false dependencies introduced due to SBID aliasing.

Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25514>

---

 src/intel/compiler/brw_fs_scoreboard.cpp | 8 +++++---
 src/intel/compiler/brw_ir_fs.h           | 2 +-
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/intel/compiler/brw_fs_scoreboard.cpp 
b/src/intel/compiler/brw_fs_scoreboard.cpp
index 6e2ad22ee13..0da4ee8d0c5 100644
--- a/src/intel/compiler/brw_fs_scoreboard.cpp
+++ b/src/intel/compiler/brw_fs_scoreboard.cpp
@@ -127,6 +127,8 @@ namespace {
          return TGL_PIPE_NONE;
       else if (devinfo->verx10 < 125)
          return TGL_PIPE_FLOAT;
+      else if (inst->is_math() && devinfo->ver >= 20)
+         return TGL_PIPE_MATH;
       else if (inst->opcode == SHADER_OPCODE_MOV_INDIRECT ||
                inst->opcode == SHADER_OPCODE_BROADCAST ||
                inst->opcode == SHADER_OPCODE_SHUFFLE ||
@@ -1016,8 +1018,8 @@ namespace {
       const ordered_address jp = p ? ordered_address(p, jps[ip].jp[IDX(p)]) :
                                      ordered_address();
       const bool is_ordered = ordered_unit(devinfo, inst, IDX(TGL_PIPE_ALL));
-      const bool uses_math_pipe =
-         inst->is_math() ||
+      const bool is_unordered_math =
+         (inst->is_math() && devinfo->ver < 20) ||
          (devinfo->has_64bit_float_via_math_pipe &&
           (get_exec_type(inst) == BRW_REGISTER_TYPE_DF ||
            inst->dst.type == BRW_REGISTER_TYPE_DF));
@@ -1029,7 +1031,7 @@ namespace {
       for (unsigned i = 0; i < inst->sources; i++) {
          const dependency rd_dep =
             (inst->is_payload(i) ||
-             uses_math_pipe) ? dependency(TGL_SBID_SRC, ip, exec_all) :
+             is_unordered_math) ? dependency(TGL_SBID_SRC, ip, exec_all) :
             is_ordered ? dependency(TGL_REGDIST_SRC, jp, exec_all) :
             dependency::done;
 
diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h
index 7ef815a7601..7bf418e0735 100644
--- a/src/intel/compiler/brw_ir_fs.h
+++ b/src/intel/compiler/brw_ir_fs.h
@@ -575,7 +575,7 @@ is_send(const fs_inst *inst)
 static inline bool
 is_unordered(const intel_device_info *devinfo, const fs_inst *inst)
 {
-   return is_send(inst) || inst->is_math() ||
+   return is_send(inst) || (devinfo->ver < 20 && inst->is_math()) ||
           (devinfo->has_64bit_float_via_math_pipe &&
            (get_exec_type(inst) == BRW_REGISTER_TYPE_DF ||
             inst->dst.type == BRW_REGISTER_TYPE_DF));

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