Module: Mesa
Branch: main
Commit: fcd025c1ce658f1efd18b2e0072ef5c82862db2b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fcd025c1ce658f1efd18b2e0072ef5c82862db2b
Author: Caio Oliveira <caio.olive...@intel.com>
Date: Mon Oct 9 08:23:53 2023 -0700
intel/compiler: Remove is_tex()
The current name doesn't cover all the tex related instructions and
in all usages, we already have a switch statement to dispatch
per instruction type, so is more natural to list the instructions we
care there.
In fs::is_send_from_grf() we can simply ignore them since the
instructions are either lowered directly to SEND (Gfx7+) or use
MRF (Gfx6-).
With this change, the fs_inst::size_read() generated code gets
simplified (the "tex" entries get added to the switch jump table
in gcc) and the default case loses the conditional handling tex.
This reduces shader compilation time, as illustrated by replaying
fossils (tested on my TGL laptop):
```
// Rise of the Tomb Raider (N=13)
Difference at 95.0% confidence
-1.32231 +/- 0.0170138
-4.37605% +/- 0.0563054%
(Student's t, pooled s = 0.0210159)
// Cyberpunk 2077 (N=7)
Difference at 95.0% confidence
-3.64 +/- 0.114993
-2.95188% +/- 0.0932544%
(Student's t, pooled s = 0.09873)
```
Suggested-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25721>
---
src/intel/compiler/brw_fs.cpp | 46 +++++++++++++++++++++++++++++++--------
src/intel/compiler/brw_ir.h | 1 -
src/intel/compiler/brw_shader.cpp | 21 ------------------
src/intel/compiler/brw_vec4.cpp | 19 +++++++++++++---
4 files changed, 53 insertions(+), 34 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index f46f394658b..62407eb47a2 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -243,9 +243,6 @@ fs_inst::is_send_from_grf() const
case FS_OPCODE_FB_READ:
return src[0].file == VGRF;
default:
- if (is_tex())
- return src[0].file == VGRF;
-
return false;
}
}
@@ -309,16 +306,29 @@ fs_inst::is_payload(unsigned arg) const
case SHADER_OPCODE_INTERLOCK:
case SHADER_OPCODE_MEMORY_FENCE:
case SHADER_OPCODE_BARRIER:
+ case SHADER_OPCODE_TEX:
+ case FS_OPCODE_TXB:
+ case SHADER_OPCODE_TXD:
+ case SHADER_OPCODE_TXF:
+ case SHADER_OPCODE_TXF_LZ:
+ case SHADER_OPCODE_TXF_CMS:
+ case SHADER_OPCODE_TXF_CMS_W:
+ case SHADER_OPCODE_TXF_UMS:
+ case SHADER_OPCODE_TXF_MCS:
+ case SHADER_OPCODE_TXL:
+ case SHADER_OPCODE_TXL_LZ:
+ case SHADER_OPCODE_TXS:
+ case SHADER_OPCODE_LOD:
+ case SHADER_OPCODE_TG4:
+ case SHADER_OPCODE_TG4_OFFSET:
+ case SHADER_OPCODE_SAMPLEINFO:
return arg == 0;
case SHADER_OPCODE_SEND:
return arg == 2 || arg == 3;
default:
- if (is_tex())
- return arg == 0;
- else
- return false;
+ return false;
}
}
@@ -910,10 +920,28 @@ fs_inst::size_read(int arg) const
}
break;
- default:
- if (arg == 0 && src[0].file == VGRF && is_tex())
+ case SHADER_OPCODE_TEX:
+ case FS_OPCODE_TXB:
+ case SHADER_OPCODE_TXD:
+ case SHADER_OPCODE_TXF:
+ case SHADER_OPCODE_TXF_LZ:
+ case SHADER_OPCODE_TXF_CMS:
+ case SHADER_OPCODE_TXF_CMS_W:
+ case SHADER_OPCODE_TXF_UMS:
+ case SHADER_OPCODE_TXF_MCS:
+ case SHADER_OPCODE_TXL:
+ case SHADER_OPCODE_TXL_LZ:
+ case SHADER_OPCODE_TXS:
+ case SHADER_OPCODE_LOD:
+ case SHADER_OPCODE_TG4:
+ case SHADER_OPCODE_TG4_OFFSET:
+ case SHADER_OPCODE_SAMPLEINFO:
+ if (arg == 0 && src[0].file == VGRF)
return mlen * REG_SIZE;
break;
+
+ default:
+ break;
}
switch (src[arg].file) {
diff --git a/src/intel/compiler/brw_ir.h b/src/intel/compiler/brw_ir.h
index a123a03ba49..b77668a5e46 100644
--- a/src/intel/compiler/brw_ir.h
+++ b/src/intel/compiler/brw_ir.h
@@ -96,7 +96,6 @@ struct bblock_t;
struct backend_instruction : public exec_node {
bool is_3src(const struct brw_compiler *compiler) const;
- bool is_tex() const;
bool is_math() const;
bool is_control_flow_begin() const;
bool is_control_flow_end() const;
diff --git a/src/intel/compiler/brw_shader.cpp
b/src/intel/compiler/brw_shader.cpp
index 423c1976b7c..c0a266009b7 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -849,27 +849,6 @@ backend_instruction::is_3src(const struct brw_compiler
*compiler) const
return ::is_3src(&compiler->isa, opcode);
}
-bool
-backend_instruction::is_tex() const
-{
- return (opcode == SHADER_OPCODE_TEX ||
- opcode == FS_OPCODE_TXB ||
- opcode == SHADER_OPCODE_TXD ||
- opcode == SHADER_OPCODE_TXF ||
- opcode == SHADER_OPCODE_TXF_LZ ||
- opcode == SHADER_OPCODE_TXF_CMS ||
- opcode == SHADER_OPCODE_TXF_CMS_W ||
- opcode == SHADER_OPCODE_TXF_UMS ||
- opcode == SHADER_OPCODE_TXF_MCS ||
- opcode == SHADER_OPCODE_TXL ||
- opcode == SHADER_OPCODE_TXL_LZ ||
- opcode == SHADER_OPCODE_TXS ||
- opcode == SHADER_OPCODE_LOD ||
- opcode == SHADER_OPCODE_TG4 ||
- opcode == SHADER_OPCODE_TG4_OFFSET ||
- opcode == SHADER_OPCODE_SAMPLEINFO);
-}
-
bool
backend_instruction::is_math() const
{
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 57449a61a02..67baec9f44a 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -290,6 +290,22 @@ vec4_instruction::can_do_writemask(const struct
intel_device_info *devinfo)
case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
case VEC4_OPCODE_URB_READ:
case SHADER_OPCODE_MOV_INDIRECT:
+ case SHADER_OPCODE_TEX:
+ case FS_OPCODE_TXB:
+ case SHADER_OPCODE_TXD:
+ case SHADER_OPCODE_TXF:
+ case SHADER_OPCODE_TXF_LZ:
+ case SHADER_OPCODE_TXF_CMS:
+ case SHADER_OPCODE_TXF_CMS_W:
+ case SHADER_OPCODE_TXF_UMS:
+ case SHADER_OPCODE_TXF_MCS:
+ case SHADER_OPCODE_TXL:
+ case SHADER_OPCODE_TXL_LZ:
+ case SHADER_OPCODE_TXS:
+ case SHADER_OPCODE_LOD:
+ case SHADER_OPCODE_TG4:
+ case SHADER_OPCODE_TG4_OFFSET:
+ case SHADER_OPCODE_SAMPLEINFO:
return false;
default:
/* The MATH instruction on Gfx6 only executes in align1 mode, which does
@@ -298,9 +314,6 @@ vec4_instruction::can_do_writemask(const struct
intel_device_info *devinfo)
if (devinfo->ver == 6 && is_math())
return false;
- if (is_tex())
- return false;
-
return true;
}
}
