Module: Mesa Branch: main Commit: 768c5934d0d761d4f3f031f1a197b2b9a202c21f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=768c5934d0d761d4f3f031f1a197b2b9a202c21f
Author: Qiang Yu <yuq...@gmail.com> Date: Thu Nov 9 15:17:28 2023 +0800 radeonsi: fix piglit image coherency test when use aco spec@arb_shader_image_load_store@coherency will write to coherent image in tess shader and read it in fragmant shader. There is a geometry shader in between. When lower ngg for the geometry shader, it will wait memory writes before pos0 export if there's no param output to prevent fragment shader start early and read any previous memory writes. We need to update the memory writes info of GS with ES ones because ES and GS is merged into one shader but when nir they are separated. LLVM does not have this problem because it will add memory write wait at the beginning of GS automatically. Reviewed-by: Marek Olšák <marek.ol...@amd.com> Signed-off-by: Qiang Yu <yuq...@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26122> --- src/gallium/drivers/radeonsi/si_shader.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 9590bc790a8..0d25c0c312d 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -1888,6 +1888,10 @@ static void si_lower_ngg(struct si_shader *shader, nir_shader *nir) options.has_gen_prim_query = options.has_xfb_prim_query = sel->screen->info.gfx_level >= GFX11; + /* For monolithic ES/GS to add vscnt wait when GS export pos0. */ + if (key->ge.part.gs.es) + nir->info.writes_memory |= key->ge.part.gs.es->info.base.writes_memory; + NIR_PASS_V(nir, ac_nir_lower_ngg_gs, &options); }
