Module: Mesa Branch: main Commit: 33f430779677f0550932573e2f629a76993072af URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=33f430779677f0550932573e2f629a76993072af
Author: Samuel Pitoiset <samuel.pitoi...@gmail.com> Date: Fri Aug 25 11:04:50 2023 +0200 radv: add radv_write_timestamp() helper Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22779> --- src/amd/vulkan/radv_private.h | 2 ++ src/amd/vulkan/radv_query.c | 34 +++++++++++++++++++++------------- 2 files changed, 23 insertions(+), 13 deletions(-) diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index e8f63614f22..ff16f49da65 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2067,6 +2067,8 @@ uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer, const struct radv_ void radv_copy_buffer(struct radv_cmd_buffer *cmd_buffer, struct radeon_winsys_bo *src_bo, struct radeon_winsys_bo *dst_bo, uint64_t src_offset, uint64_t dst_offset, uint64_t size); +void radv_write_timestamp(struct radv_cmd_buffer *cmd_buffer, uint64_t va, VkPipelineStageFlags2 stage); + void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer); bool radv_get_memory_fd(struct radv_device *device, struct radv_device_memory *memory, int *pFD); void radv_free_memory(struct radv_device *device, const VkAllocationCallbacks *pAllocator, diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index 02339b508be..d99b449bb54 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -2080,6 +2080,26 @@ radv_CmdEndQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, } } +void +radv_write_timestamp(struct radv_cmd_buffer *cmd_buffer, uint64_t va, VkPipelineStageFlags2 stage) +{ + struct radeon_cmdbuf *cs = cmd_buffer->cs; + + if (stage == VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT) { + radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); + radeon_emit(cs, COPY_DATA_COUNT_SEL | COPY_DATA_WR_CONFIRM | COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) | + COPY_DATA_DST_SEL(V_370_MEM)); + radeon_emit(cs, 0); + radeon_emit(cs, 0); + radeon_emit(cs, va); + radeon_emit(cs, va >> 32); + } else { + si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, cmd_buffer->qf, + V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_TIMESTAMP, va, 0, + cmd_buffer->gfx9_eop_bug_va); + } +} + VKAPI_ATTR void VKAPI_CALL radv_CmdWriteTimestamp2(VkCommandBuffer commandBuffer, VkPipelineStageFlags2 stage, VkQueryPool queryPool, uint32_t query) @@ -2106,19 +2126,7 @@ radv_CmdWriteTimestamp2(VkCommandBuffer commandBuffer, VkPipelineStageFlags2 sta ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 28 * num_queries); for (unsigned i = 0; i < num_queries; i++) { - if (stage == VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT) { - radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); - radeon_emit(cs, COPY_DATA_COUNT_SEL | COPY_DATA_WR_CONFIRM | COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) | - COPY_DATA_DST_SEL(V_370_MEM)); - radeon_emit(cs, 0); - radeon_emit(cs, 0); - radeon_emit(cs, query_va); - radeon_emit(cs, query_va >> 32); - } else { - si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, cmd_buffer->qf, - V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_TIMESTAMP, query_va, 0, - cmd_buffer->gfx9_eop_bug_va); - } + radv_write_timestamp(cmd_buffer, query_va, stage); query_va += pool->stride; }
