Mesa (main): anv: Write timestamp using MI_FLUSH_DW on blitter

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Module: Mesa
Branch: main
Commit: 8c9a7f77303b5acb4555a8c41b897da891fbe2da
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c9a7f77303b5acb4555a8c41b897da891fbe2da

Author: Sagar Ghuge <sagar.gh...@intel.com>
Date:   Wed Nov  8 17:33:40 2023 -0800

anv: Write timestamp using MI_FLUSH_DW on blitter

On Blitter engine, we don't support PIPE_CONTROL, we have to update
memory locations using the MI_FLUSH_DW command.

v2:
- Handle video queue (Lionel)

Fixes: 056b0cb87f2 ("anv: add video engine support in various places")
Fixes: 5112b421462 ("anv: Handle end of pipe with MI_FLUSH_DW on transfer 
queue")

Signed-off-by: Sagar Ghuge <sagar.gh...@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26121>

---

 src/intel/vulkan/genX_cmd_buffer.c |  6 ++++--
 src/intel/vulkan/genX_query.c      | 22 ++++++++++++++++------
 2 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 6ca022fdca9..4985d40a85f 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -8164,7 +8164,8 @@ void genX(cmd_emit_timestamp)(struct anv_batch *batch,
     * ANV_TIMESTAMP_REWRITE_COMPUTE_WALKER capture type are not set for
     * transfer queue.
     */
-   if (batch->engine_class == INTEL_ENGINE_CLASS_COPY) {
+   if ((batch->engine_class == INTEL_ENGINE_CLASS_COPY) ||
+       (batch->engine_class == INTEL_ENGINE_CLASS_VIDEO)) {
       assert(type != ANV_TIMESTAMP_CAPTURE_AT_CS_STALL &&
              type != ANV_TIMESTAMP_REWRITE_COMPUTE_WALKER);
    }
@@ -8178,7 +8179,8 @@ void genX(cmd_emit_timestamp)(struct anv_batch *batch,
    }
 
    case ANV_TIMESTAMP_CAPTURE_END_OF_PIPE: {
-      if (batch->engine_class == INTEL_ENGINE_CLASS_COPY) {
+      if ((batch->engine_class == INTEL_ENGINE_CLASS_COPY) ||
+          (batch->engine_class == INTEL_ENGINE_CLASS_VIDEO)) {
          anv_batch_emit(batch, GENX(MI_FLUSH_DW), fd) {
             fd.PostSyncOperation = WriteTimestamp;
             fd.Address = addr;
diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c
index 0f387246f46..6fc29b1bd6e 100644
--- a/src/intel/vulkan/genX_query.c
+++ b/src/intel/vulkan/genX_query.c
@@ -1403,13 +1403,23 @@ void genX(CmdWriteTimestamp2)(
 
       bool cs_stall_needed =
          (GFX_VER == 9 && cmd_buffer->device->info->gt == 4);
-      genx_batch_emit_pipe_control_write
-         (&cmd_buffer->batch, cmd_buffer->device->info,
-          cmd_buffer->state.current_pipeline, WriteTimestamp,
-          anv_address_add(query_addr, 8), 0,
-          cs_stall_needed ? ANV_PIPE_CS_STALL_BIT : 0);
 
-      emit_query_pc_availability(cmd_buffer, query_addr, true);
+      if (anv_cmd_buffer_is_blitter_queue(cmd_buffer) ||
+          anv_cmd_buffer_is_video_queue(cmd_buffer)) {
+         anv_batch_emit(&cmd_buffer->batch, GENX(MI_FLUSH_DW), dw) {
+            dw.Address = anv_address_add(query_addr, 8);
+            dw.PostSyncOperation = WriteTimestamp;
+         }
+         emit_query_mi_flush_availability(cmd_buffer, query_addr, true);
+      } else {
+         genx_batch_emit_pipe_control_write
+            (&cmd_buffer->batch, cmd_buffer->device->info,
+             cmd_buffer->state.current_pipeline, WriteTimestamp,
+             anv_address_add(query_addr, 8), 0,
+             cs_stall_needed ? ANV_PIPE_CS_STALL_BIT : 0);
+         emit_query_pc_availability(cmd_buffer, query_addr, true);
+      }
+
    }