Module: Mesa Branch: main Commit: 1cfb0ae92cdb2b6b248aebd528f0c28d238f7930 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1cfb0ae92cdb2b6b248aebd528f0c28d238f7930
Author: Connor Abbott <cwabbo...@gmail.com> Date: Mon Feb 4 12:47:53 2019 +0100 nir: Add quad vote intrinsics Both Intel and AMD have special hardware support for these. Reviewed-by: Ian Romanick <ian.d.roman...@intel.com> Reviewed-by: Georg Lehmann <dadschoo...@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/218> --- src/compiler/nir/nir_divergence_analysis.c | 2 ++ src/compiler/nir/nir_gather_info.c | 2 ++ src/compiler/nir/nir_intrinsics.py | 6 ++++++ 3 files changed, 10 insertions(+) diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index 91a5135deb2..9e295c01624 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -420,6 +420,8 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) case nir_intrinsic_quad_swap_horizontal: case nir_intrinsic_quad_swap_vertical: case nir_intrinsic_quad_swap_diagonal: + case nir_intrinsic_quad_vote_any: + case nir_intrinsic_quad_vote_all: case nir_intrinsic_load_deref: case nir_intrinsic_load_shared: case nir_intrinsic_load_shared2_amd: diff --git a/src/compiler/nir/nir_gather_info.c b/src/compiler/nir/nir_gather_info.c index 040949fe1b4..d363d176343 100644 --- a/src/compiler/nir/nir_gather_info.c +++ b/src/compiler/nir/nir_gather_info.c @@ -724,6 +724,8 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader, } break; + case nir_intrinsic_quad_vote_any: + case nir_intrinsic_quad_vote_all: case nir_intrinsic_quad_broadcast: case nir_intrinsic_quad_swap_horizontal: case nir_intrinsic_quad_swap_vertical: diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 93b8b5280cf..bc1f81ed0cb 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -499,6 +499,12 @@ intrinsic("quad_swap_horizontal", src_comp=[0], dest_comp=0, bit_sizes=src0, fla intrinsic("quad_swap_vertical", src_comp=[0], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) intrinsic("quad_swap_diagonal", src_comp=[0], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) +# Similar to vote_any and vote_all, but per-quad instead of per-wavefront. +# Equivalent to subgroupOr(val, 4) and subgroupAnd(val, 4) assuming val is +# boolean. +intrinsic("quad_vote_any", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) +intrinsic("quad_vote_all", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) + # Rotate operation from SPIR-V: SpvOpGroupNonUniformRotateKHR. intrinsic("rotate", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, indices=[EXECUTION_SCOPE, CLUSTER_SIZE], flags=[CAN_ELIMINATE]);
