Module: Mesa Branch: main Commit: ec3f8c0d42f9e0a742c7aeb835aa56155ebb1faa URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec3f8c0d42f9e0a742c7aeb835aa56155ebb1faa
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com> Date: Wed Nov 8 12:14:09 2023 +0200 intel/blorp: move Wa_18019816803 out of blorp code The driver already need to track this WA for blorp. We can completely remove any blorp code dealing with this and instead have the flush required by the workaround be combined with potential other flushes the driver already has to insert before blorp operations. Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Reviewed-by: Ian Romanick <ian.d.roman...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26247> --- src/gallium/drivers/iris/iris_blorp.c | 15 ++++++++++----- src/intel/blorp/blorp.h | 3 --- src/intel/blorp/blorp_genX_exec.h | 12 ------------ src/intel/vulkan/genX_blorp_exec.c | 11 ++++++++++- 4 files changed, 20 insertions(+), 21 deletions(-) diff --git a/src/gallium/drivers/iris/iris_blorp.c b/src/gallium/drivers/iris/iris_blorp.c index 63f212976ca..5e8b35815d8 100644 --- a/src/gallium/drivers/iris/iris_blorp.c +++ b/src/gallium/drivers/iris/iris_blorp.c @@ -287,6 +287,7 @@ iris_blorp_exec_render(struct blorp_batch *blorp_batch, { struct iris_context *ice = blorp_batch->blorp->driver_ctx; struct iris_batch *batch = blorp_batch->driver_batch; + uint32_t pc_flags = 0; #if GFX_VER >= 11 /* The PIPE_CONTROL command description says: @@ -297,10 +298,8 @@ iris_blorp_exec_render(struct blorp_batch *blorp_batch, * is set due to new association of BTI, PS Scoreboard Stall bit must * be set in this packet." */ - iris_emit_pipe_control_flush(batch, - "workaround: RT BTI change [blorp]", - PIPE_CONTROL_RENDER_TARGET_FLUSH | - PIPE_CONTROL_STALL_AT_SCOREBOARD); + pc_flags = PIPE_CONTROL_RENDER_TARGET_FLUSH | + PIPE_CONTROL_STALL_AT_SCOREBOARD; #endif /* Check if blorp ds state matches ours. */ @@ -308,11 +307,17 @@ iris_blorp_exec_render(struct blorp_batch *blorp_batch, const bool blorp_ds_state = params->depth.enabled || params->stencil.enabled; if (ice->state.ds_write_state != blorp_ds_state) { - blorp_batch->flags |= BLORP_BATCH_NEED_PSS_STALL_SYNC; + pc_flags |= PIPE_CONTROL_PSS_STALL_SYNC; ice->state.ds_write_state = blorp_ds_state; } } + if (pc_flags != 0) { + iris_emit_pipe_control_flush(batch, + "workaround: prior to [blorp]", + pc_flags); + } + if (params->depth.enabled && !(blorp_batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL)) genX(emit_depth_state_workarounds)(ice, batch, ¶ms->depth.surf); diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h index aae86d23173..6da62f07839 100644 --- a/src/intel/blorp/blorp.h +++ b/src/intel/blorp/blorp.h @@ -111,9 +111,6 @@ enum blorp_batch_flags { /** Use the hardware blitter to perform any operations in this batch */ BLORP_BATCH_USE_BLITTER = (1 << 4), - - /** Need a PSS Stall Sync, Wa_18019816803. */ - BLORP_BATCH_NEED_PSS_STALL_SYNC = (1 << 5), }; struct blorp_batch { diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index 0212abdcbe1..f0add131e45 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -1259,18 +1259,6 @@ blorp_emit_depth_stencil_state(struct blorp_batch *batch, return 0; GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dw, &ds); - -#if GFX_VERx10 >= 125 - /* Check if need PSS Stall sync. */ - if (intel_needs_workaround(batch->blorp->compiler->devinfo, 18019816803) && - batch->flags & BLORP_BATCH_NEED_PSS_STALL_SYNC) { - blorp_emit(batch, GENX(PIPE_CONTROL), pc) { - pc.PSSStallSyncEnable = true; - } - batch->flags &= ~BLORP_BATCH_NEED_PSS_STALL_SYNC; - } -#endif - #else uint32_t offset; void *state = blorp_alloc_dynamic_state(batch, diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c index f3a188f6840..a7a9024df2c 100644 --- a/src/intel/vulkan/genX_blorp_exec.c +++ b/src/intel/vulkan/genX_blorp_exec.c @@ -309,9 +309,18 @@ blorp_exec_on_render(struct blorp_batch *batch, if (intel_needs_workaround(cmd_buffer->device->info, 18019816803)) { bool blorp_ds_state = params->depth.enabled || params->stencil.enabled; if (cmd_buffer->state.gfx.ds_write_state != blorp_ds_state) { - batch->flags |= BLORP_BATCH_NEED_PSS_STALL_SYNC; + /* Flag the change in ds_write_state so that the next pipeline use + * will trigger a PIPE_CONTROL too. + */ cmd_buffer->state.gfx.ds_write_state = blorp_ds_state; BITSET_SET(hw_state->dirty, ANV_GFX_STATE_WA_18019816803); + + /* Add the stall that will flush prior to the blorp operation by + * genX(cmd_buffer_apply_pipe_flushes) + */ + anv_add_pending_pipe_bits(cmd_buffer, + ANV_PIPE_PSS_STALL_SYNC_BIT, + "Wa_18019816803"); } } #endif
