Module: Mesa Branch: main Commit: 4d2a3b95730c4781234096778043f987234b6a4c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4d2a3b95730c4781234096778043f987234b6a4c
Author: Rhys Perry <pendingchao...@gmail.com> Date: Wed Oct 18 15:34:45 2023 +0100 radv: add radv_disable_trunc_coord option Signed-off-by: Rhys Perry <pendingchao...@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> Cc: mesa-stable Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25911> --- src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c | 9 +++++---- src/amd/vulkan/radv_device.c | 14 ++++++++++++++ src/amd/vulkan/radv_instance.c | 3 +++ src/amd/vulkan/radv_pipeline.c | 5 ++++- src/amd/vulkan/radv_private.h | 4 ++++ src/amd/vulkan/radv_sampler.c | 5 +++-- src/amd/vulkan/radv_shader.h | 1 + src/util/driconf.h | 4 ++++ 8 files changed, 38 insertions(+), 7 deletions(-) diff --git a/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c b/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c index a5d91119b8d..210a1357f00 100644 --- a/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c +++ b/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c @@ -34,7 +34,7 @@ typedef struct { uint32_t address32_hi; bool disable_aniso_single_level; bool has_image_load_dcc_bug; - bool conformant_trunc_coord; + bool disable_tg4_trunc_coord; const struct radv_shader_args *args; const struct radv_shader_info *info; @@ -246,7 +246,7 @@ get_sampler_desc(nir_builder *b, apply_layout_state *state, nir_deref_instr *der } uint32_t dword0_mask = - tex->op == nir_texop_tg4 && !state->conformant_trunc_coord ? C_008F30_TRUNC_COORD : 0xffffffffu; + tex->op == nir_texop_tg4 && state->disable_tg4_trunc_coord ? C_008F30_TRUNC_COORD : 0xffffffffu; const uint32_t *samplers = radv_immutable_samplers(layout, binding); return nir_imm_ivec4(b, samplers[constant_index * 4 + 0] & dword0_mask, samplers[constant_index * 4 + 1], samplers[constant_index * 4 + 2], samplers[constant_index * 4 + 3]); @@ -330,7 +330,7 @@ get_sampler_desc(nir_builder *b, apply_layout_state *state, nir_deref_instr *der comp[6] = nir_iand_imm(b, comp[6], C_00A018_WRITE_COMPRESS_ENABLE); return nir_vec(b, comp, 8); - } else if (desc_type == AC_DESC_SAMPLER && tex->op == nir_texop_tg4 && !state->conformant_trunc_coord) { + } else if (desc_type == AC_DESC_SAMPLER && tex->op == nir_texop_tg4 && state->disable_tg4_trunc_coord) { nir_def *comp[4]; for (unsigned i = 0; i < 4; i++) comp[i] = nir_channel(b, desc, i); @@ -507,7 +507,8 @@ radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *device, c .address32_hi = device->physical_device->rad_info.address32_hi, .disable_aniso_single_level = device->instance->disable_aniso_single_level, .has_image_load_dcc_bug = device->physical_device->rad_info.has_image_load_dcc_bug, - .conformant_trunc_coord = device->physical_device->rad_info.conformant_trunc_coord, + .disable_tg4_trunc_coord = + !device->physical_device->rad_info.conformant_trunc_coord && !device->disable_trunc_coord, .args = args, .info = info, .layout = layout, diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 1258a5ae2e4..bc98c173207 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -726,11 +726,13 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr bool use_dgc = false; bool smooth_lines = false; bool mesh_shader_queries = false; + bool dual_src_blend = false; /* Check enabled features */ if (pCreateInfo->pEnabledFeatures) { if (pCreateInfo->pEnabledFeatures->robustBufferAccess) buffer_robustness = MAX2(buffer_robustness, RADV_BUFFER_ROBUSTNESS_1); + dual_src_blend = pCreateInfo->pEnabledFeatures->dualSrcBlend; } vk_foreach_struct_const (ext, pCreateInfo->pNext) { @@ -739,6 +741,7 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr const VkPhysicalDeviceFeatures2 *features = (const void *)ext; if (features->features.robustBufferAccess) buffer_robustness = MAX2(buffer_robustness, RADV_BUFFER_ROBUSTNESS_1); + dual_src_blend |= features->features.dualSrcBlend; break; } case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: { @@ -1147,6 +1150,17 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n", 1 << util_logbase2(device->force_aniso)); } + device->disable_trunc_coord = device->instance->disable_trunc_coord; + + if (device->instance->vk.app_info.engine_name && !strcmp(device->instance->vk.app_info.engine_name, "DXVK")) { + /* For DXVK 2.3.0 and older, use dualSrcBlend to determine if this is D3D9. */ + bool is_d3d9 = !dual_src_blend; + if (device->instance->vk.app_info.engine_version > VK_MAKE_VERSION(2, 3, 0)) + is_d3d9 = device->instance->vk.app_info.app_version & 0x1; + + device->disable_trunc_coord &= !is_d3d9; + } + if (use_perf_counters) { size_t bo_size = PERF_CTR_BO_PASS_OFFSET + sizeof(uint64_t) * PERF_CTR_MAX_PASSES; result = device->ws->buffer_create(device->ws, bo_size, 4096, RADEON_DOMAIN_GTT, diff --git a/src/amd/vulkan/radv_instance.c b/src/amd/vulkan/radv_instance.c index 57685184d69..370e16a6083 100644 --- a/src/amd/vulkan/radv_instance.c +++ b/src/amd/vulkan/radv_instance.c @@ -144,6 +144,7 @@ static const driOptionDescription radv_dri_options[] = { DRI_CONF_RADV_DISABLE_TC_COMPAT_HTILE_GENERAL(false) DRI_CONF_RADV_DISABLE_DCC(false) DRI_CONF_RADV_DISABLE_ANISO_SINGLE_LEVEL(false) + DRI_CONF_RADV_DISABLE_TRUNC_COORD(false) DRI_CONF_RADV_DISABLE_SINKING_LOAD_INPUT_FS(false) DRI_CONF_RADV_DGC(false) DRI_CONF_RADV_FLUSH_BEFORE_QUERY_COPY(false) @@ -194,6 +195,8 @@ radv_init_dri_options(struct radv_instance *instance) instance->disable_aniso_single_level = driQueryOptionb(&instance->dri_options, "radv_disable_aniso_single_level"); + instance->disable_trunc_coord = driQueryOptionb(&instance->dri_options, "radv_disable_trunc_coord"); + instance->disable_sinking_load_input_fs = driQueryOptionb(&instance->dri_options, "radv_disable_sinking_load_input_fs"); diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index a4351836e76..0e3a79f5307 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -157,6 +157,8 @@ radv_generate_pipeline_key(const struct radv_device *device, const VkPipelineSha key.disable_aniso_single_level = device->instance->disable_aniso_single_level && device->physical_device->rad_info.gfx_level < GFX8; + key.disable_trunc_coord = device->disable_trunc_coord; + key.image_2d_view_of_3d = device->image_2d_view_of_3d && device->physical_device->rad_info.gfx_level == GFX9; key.tex_non_uniform = device->instance->tex_non_uniform; @@ -626,7 +628,8 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_key NIR_PASS(_, stage->nir, ac_nir_lower_tex, &(ac_nir_lower_tex_options){ .gfx_level = gfx_level, - .lower_array_layer_round_even = !device->physical_device->rad_info.conformant_trunc_coord, + .lower_array_layer_round_even = + !device->physical_device->rad_info.conformant_trunc_coord || device->disable_trunc_coord, .fix_derivs_in_divergent_cf = fix_derivs_in_divergent_cf, .max_wqm_vgprs = 64, // TODO: improve spiller and RA support for linear VGPRs }); diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 09d7543f8d3..1cfb2af5146 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -410,6 +410,7 @@ struct radv_instance { bool disable_tc_compat_htile_in_general; bool disable_shrink_image_store; bool disable_aniso_single_level; + bool disable_trunc_coord; bool zero_vram; bool disable_sinking_load_input_fs; bool flush_before_query_copy; @@ -1054,6 +1055,9 @@ struct radv_device { /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */ int force_aniso; + /* Always disable TRUNC_COORD. */ + bool disable_trunc_coord; + struct radv_device_border_color_data border_color_data; /* Thread trace. */ diff --git a/src/amd/vulkan/radv_sampler.c b/src/amd/vulkan/radv_sampler.c index 19fb0ef44e6..baf171dd5f7 100644 --- a/src/amd/vulkan/radv_sampler.c +++ b/src/amd/vulkan/radv_sampler.c @@ -200,8 +200,9 @@ radv_init_sampler(struct radv_device *device, struct radv_sampler *sampler, cons device->physical_device->rad_info.gfx_level == GFX8 || device->physical_device->rad_info.gfx_level == GFX9; unsigned filter_mode = radv_tex_filter_mode(sampler->vk.reduction_mode); unsigned depth_compare_func = V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER; - bool trunc_coord = (pCreateInfo->minFilter == VK_FILTER_NEAREST && pCreateInfo->magFilter == VK_FILTER_NEAREST) || - device->physical_device->rad_info.conformant_trunc_coord; + bool trunc_coord = ((pCreateInfo->minFilter == VK_FILTER_NEAREST && pCreateInfo->magFilter == VK_FILTER_NEAREST) || + device->physical_device->rad_info.conformant_trunc_coord) && + !device->disable_trunc_coord; bool uses_border_color = pCreateInfo->addressModeU == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER || pCreateInfo->addressModeV == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER || pCreateInfo->addressModeW == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER; diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index ea5ab6cc888..ab0b58d87cf 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -85,6 +85,7 @@ struct radv_pipeline_key { uint32_t use_ngg : 1; uint32_t adjust_frag_coord_z : 1; uint32_t disable_aniso_single_level : 1; + uint32_t disable_trunc_coord : 1; uint32_t disable_sinking_load_input_fs : 1; uint32_t image_2d_view_of_3d : 1; uint32_t primitives_generated_query : 1; diff --git a/src/util/driconf.h b/src/util/driconf.h index 450217931b5..941d15a2f50 100644 --- a/src/util/driconf.h +++ b/src/util/driconf.h @@ -649,6 +649,10 @@ DRI_CONF_OPT_B(radv_disable_aniso_single_level, def, \ "Disable anisotropic filtering for single level images") +#define DRI_CONF_RADV_DISABLE_TRUNC_COORD(def) \ + DRI_CONF_OPT_B(radv_disable_trunc_coord, def, \ + "Disable TRUNC_COORD to use D3D10/11/12 point sampling behaviour. This has special behaviour for DXVK.") + #define DRI_CONF_RADV_DISABLE_SINKING_LOAD_INPUT_FS(def) \ DRI_CONF_OPT_B(radv_disable_sinking_load_input_fs, def, \ "Disable sinking load inputs for fragment shaders")
