Module: Mesa Branch: main Commit: 8c79d616bd67f1e73e0a8c2c529dfe43f40be166 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c79d616bd67f1e73e0a8c2c529dfe43f40be166
Author: Faith Ekstrand <faith.ekstr...@collabora.com> Date: Fri Nov 17 11:28:26 2023 -0600 nak: Add builder helpers for a few ops Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26264> --- src/nouveau/compiler/nak_builder.rs | 31 +++++++++++++++++++++++++++++++ src/nouveau/compiler/nak_from_nir.rs | 33 ++++----------------------------- 2 files changed, 35 insertions(+), 29 deletions(-) diff --git a/src/nouveau/compiler/nak_builder.rs b/src/nouveau/compiler/nak_builder.rs index 93ddd3e53d1..31cb220b6c8 100644 --- a/src/nouveau/compiler/nak_builder.rs +++ b/src/nouveau/compiler/nak_builder.rs @@ -76,6 +76,16 @@ pub trait SSABuilder: Builder { dst } + fn fmnmx(&mut self, x: Src, y: Src, min: Src) -> SSARef { + let dst = self.alloc_ssa(RegFile::GPR, 1); + self.push_op(OpFMnMx { + dst: dst.into(), + srcs: [x, y], + min: min, + }); + dst + } + fn fmul(&mut self, x: Src, y: Src) -> SSARef { let dst = self.alloc_ssa(RegFile::GPR, 1); self.push_op(OpFMul { @@ -127,6 +137,27 @@ pub trait SSABuilder: Builder { dst } + fn imnmx(&mut self, tp: IntCmpType, x: Src, y: Src, min: Src) -> SSARef { + let dst = self.alloc_ssa(RegFile::GPR, 1); + self.push_op(OpIMnMx { + dst: dst.into(), + cmp_type: tp, + srcs: [x, y], + min: min, + }); + dst + } + + fn imul(&mut self, x: Src, y: Src) -> SSARef { + let dst = self.alloc_ssa(RegFile::GPR, 1); + self.push_op(OpIMad { + dst: dst.into(), + srcs: [x, y, 0.into()], + signed: false, + }); + dst + } + fn ineg(&mut self, i: Src) -> SSARef { let dst = self.alloc_ssa(RegFile::GPR, 1); self.push_op(OpINeg { diff --git a/src/nouveau/compiler/nak_from_nir.rs b/src/nouveau/compiler/nak_from_nir.rs index 5ec911cb890..4b97babb74c 100644 --- a/src/nouveau/compiler/nak_from_nir.rs +++ b/src/nouveau/compiler/nak_from_nir.rs @@ -466,23 +466,11 @@ impl<'a> ShaderFromNir<'a> { } nir_op_fmax => { assert!(alu.def.bit_size() == 32); - let dst = b.alloc_ssa(RegFile::GPR, 1); - b.push_op(OpFMnMx { - dst: dst.into(), - srcs: [srcs[0], srcs[1]], - min: SrcRef::False.into(), - }); - dst + b.fmnmx(srcs[0], srcs[1], false.into()) } nir_op_fmin => { assert!(alu.def.bit_size() == 32); - let dst = b.alloc_ssa(RegFile::GPR, 1); - b.push_op(OpFMnMx { - dst: dst.into(), - srcs: [srcs[0], srcs[1]], - min: SrcRef::True.into(), - }); - dst + b.fmnmx(srcs[0], srcs[1], true.into()) } nir_op_fmul => { assert!(alu.def.bit_size() == 32); @@ -639,24 +627,11 @@ impl<'a> ShaderFromNir<'a> { _ => panic!("Not an integer min/max"), }; assert!(alu.def.bit_size() == 32); - let dst = b.alloc_ssa(RegFile::GPR, 1); - b.push_op(OpIMnMx { - dst: dst.into(), - cmp_type: tp, - srcs: [srcs[0], srcs[1]], - min: min.into(), - }); - dst + b.imnmx(tp, srcs[0], srcs[1], min.into()) } nir_op_imul => { assert!(alu.def.bit_size() == 32); - let dst = b.alloc_ssa(RegFile::GPR, 1); - b.push_op(OpIMad { - dst: dst.into(), - srcs: [srcs[0], srcs[1], 0.into()], - signed: false, - }); - dst + b.imul(srcs[0], srcs[1]) } nir_op_imul_2x32_64 | nir_op_umul_2x32_64 => { let dst = b.alloc_ssa(RegFile::GPR, 2);
