Module: Mesa Branch: main Commit: ec43c20182b3742934defbe67ea1f0fc902e85d7 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec43c20182b3742934defbe67ea1f0fc902e85d7
Author: Tapani Pälli <tapani.pa...@intel.com> Date: Wed Nov 15 11:07:08 2023 +0200 anv: implement dummy blit for Wa_16018063123 Insert a dummy blit prior to MI_ARB_CHECK, MI_SEMAPHORE_WAIT, MI_FLUSH_DW submitted on the copy engine. Signed-off-by: Tapani Pälli <tapani.pa...@intel.com> Reviewed-by: Sagar Ghuge <sagar.gh...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26209> --- src/intel/vulkan/anv_genX.h | 3 +++ src/intel/vulkan/genX_cmd_buffer.c | 34 ++++++++++++++++++++++++++++++++++ src/intel/vulkan/genX_query.c | 5 +++++ 3 files changed, 42 insertions(+) diff --git a/src/intel/vulkan/anv_genX.h b/src/intel/vulkan/anv_genX.h index 745a5d38907..88770f153b2 100644 --- a/src/intel/vulkan/anv_genX.h +++ b/src/intel/vulkan/anv_genX.h @@ -185,6 +185,9 @@ genX(batch_emit_post_3dprimitive_was)(struct anv_batch *batch, uint32_t primitive_topology, uint32_t vertex_count); +void genX(batch_emit_fast_color_dummy_blit)(struct anv_batch *batch, + struct anv_device *device); + VkPolygonMode genX(raster_polygon_mode)(const struct anv_graphics_pipeline *pipeline, VkPolygonMode polygon_mode, diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 5c83f09aeef..be7f92352e5 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -4016,6 +4016,11 @@ cmd_buffer_barrier_blitter(struct anv_cmd_buffer *cmd_buffer, } if (flush_ccs || flush_llc) { + /* Wa_16018063123 - emit fast color dummy blit before MI_FLUSH_DW. */ + if (intel_needs_workaround(cmd_buffer->device->info, 16018063123)) { + genX(batch_emit_fast_color_dummy_blit)(&cmd_buffer->batch, + cmd_buffer->device); + } anv_batch_emit(&cmd_buffer->batch, GENX(MI_FLUSH_DW), fd) { fd.FlushCCS = flush_ccs; fd.FlushLLC = flush_llc; @@ -8246,6 +8251,9 @@ void genX(cmd_emit_timestamp)(struct anv_batch *batch, case ANV_TIMESTAMP_CAPTURE_END_OF_PIPE: { if ((batch->engine_class == INTEL_ENGINE_CLASS_COPY) || (batch->engine_class == INTEL_ENGINE_CLASS_VIDEO)) { + /* Wa_16018063123 - emit fast color dummy blit before MI_FLUSH_DW. */ + if (intel_needs_workaround(device->info, 16018063123)) + genX(batch_emit_fast_color_dummy_blit)(batch, device); anv_batch_emit(batch, GENX(MI_FLUSH_DW), fd) { fd.PostSyncOperation = WriteTimestamp; fd.Address = addr; @@ -8325,6 +8333,27 @@ genX(batch_emit_post_3dprimitive_was)(struct anv_batch *batch, #endif } +/* Wa_16018063123 */ +ALWAYS_INLINE void +genX(batch_emit_fast_color_dummy_blit)(struct anv_batch *batch, + struct anv_device *device) +{ +#if GFX_VERx10 >= 125 + anv_batch_emit(batch, GENX(XY_FAST_COLOR_BLT), blt) { + blt.DestinationBaseAddress = device->workaround_address; + blt.DestinationMOCS = device->isl_dev.mocs.blitter_dst; + blt.DestinationPitch = 63; + blt.DestinationX2 = 1; + blt.DestinationY2 = 4; + blt.DestinationSurfaceWidth = 1; + blt.DestinationSurfaceHeight = 4; + blt.DestinationSurfaceType = XY_SURFTYPE_2D; + blt.DestinationSurfaceQPitch = 4; + blt.DestinationTiling = XY_TILE_LINEAR; + } +#endif +} + struct anv_state genX(cmd_buffer_begin_companion_rcs_syncpoint)( struct anv_cmd_buffer *cmd_buffer) @@ -8357,6 +8386,11 @@ genX(cmd_buffer_begin_companion_rcs_syncpoint)( "post main cmd buffer invalidate"); genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); } else if (anv_cmd_buffer_is_blitter_queue(cmd_buffer)) { + /* Wa_16018063123 - emit fast color dummy blit before MI_FLUSH_DW. */ + if (intel_needs_workaround(cmd_buffer->device->info, 16018063123)) { + genX(batch_emit_fast_color_dummy_blit)(&cmd_buffer->batch, + cmd_buffer->device); + } anv_batch_emit(&cmd_buffer->batch, GENX(MI_FLUSH_DW), fd) { fd.FlushCCS = true; /* Maybe handle Flush LLC */ } diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c index 6fc29b1bd6e..fcd92ec8a07 100644 --- a/src/intel/vulkan/genX_query.c +++ b/src/intel/vulkan/genX_query.c @@ -1406,6 +1406,11 @@ void genX(CmdWriteTimestamp2)( if (anv_cmd_buffer_is_blitter_queue(cmd_buffer) || anv_cmd_buffer_is_video_queue(cmd_buffer)) { + /* Wa_16018063123 - emit fast color dummy blit before MI_FLUSH_DW. */ + if (intel_needs_workaround(cmd_buffer->device->info, 16018063123)) { + genX(batch_emit_fast_color_dummy_blit)(&cmd_buffer->batch, + cmd_buffer->device); + } anv_batch_emit(&cmd_buffer->batch, GENX(MI_FLUSH_DW), dw) { dw.Address = anv_address_add(query_addr, 8); dw.PostSyncOperation = WriteTimestamp;
