Module: Mesa Branch: main Commit: 40c96ff6ea4736a326c198c5cfc779af5e9d3b4c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=40c96ff6ea4736a326c198c5cfc779af5e9d3b4c
Author: Faith Ekstrand <faith.ekstr...@collabora.com> Date: Tue Nov 28 10:39:18 2023 -0600 nak: Add a barrier register file Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26463> --- src/nouveau/compiler/nak_calc_instr_deps.rs | 8 ++++++ src/nouveau/compiler/nak_ir.rs | 41 ++++++++++++++++++++++++----- src/nouveau/compiler/nak_legalize.rs | 1 + src/nouveau/compiler/nak_opt_copy_prop.rs | 1 + src/nouveau/compiler/nak_opt_lop.rs | 2 +- 5 files changed, 46 insertions(+), 7 deletions(-) diff --git a/src/nouveau/compiler/nak_calc_instr_deps.rs b/src/nouveau/compiler/nak_calc_instr_deps.rs index 63acac02e5c..9395efc3968 100644 --- a/src/nouveau/compiler/nak_calc_instr_deps.rs +++ b/src/nouveau/compiler/nak_calc_instr_deps.rs @@ -74,6 +74,7 @@ impl<T> Index<RegRef> for RegTracker<T> { RegFile::UGPR => &self.ureg[range], RegFile::Pred => &self.pred[range], RegFile::UPred => &self.upred[range], + RegFile::Bar => &[], // Barriers have a HW scoreboard RegFile::Mem => panic!("Not a register"), } } @@ -92,6 +93,7 @@ impl<T> IndexMut<RegRef> for RegTracker<T> { RegFile::UGPR => &mut self.ureg[range], RegFile::Pred => &mut self.pred[range], RegFile::UPred => &mut self.upred[range], + RegFile::Bar => &mut [], // Barriers have a HW scoreboard RegFile::Mem => panic!("Not a register"), } } @@ -244,6 +246,9 @@ fn assign_barriers(f: &mut Function) { } for src in instr.srcs() { if let SrcRef::Reg(reg) = &src.src_ref { + if reg.file() == RegFile::Bar { + continue; + } for c in 0..reg.comps() { srcs.insert(reg.comp(c)); } @@ -253,6 +258,9 @@ fn assign_barriers(f: &mut Function) { let mut dsts = HashSet::new(); for dst in instr.dsts() { if let Dst::Reg(reg) = dst { + if reg.file() == RegFile::Bar { + continue; + } for c in 0..reg.comps() { dsts.insert(reg.comp(c)); // Remove any sources which this instruction overwrites. diff --git a/src/nouveau/compiler/nak_ir.rs b/src/nouveau/compiler/nak_ir.rs index a26a95b4262..75bc352b2c0 100644 --- a/src/nouveau/compiler/nak_ir.rs +++ b/src/nouveau/compiler/nak_ir.rs @@ -72,20 +72,25 @@ pub enum RegFile { /// Uniform predicate registers are 1 bit and uniform across a wave. UPred = 3, + /// The barrier register file + /// + /// This is a lane mask used for wave re-convergence instructions. + Bar = 4, + /// The memory register file /// /// This is a virtual register file for things which will get spilled to /// local memory. Each memory location is 32 bits per SIMT channel. - Mem = 4, + Mem = 5, } -const NUM_REG_FILES: usize = 5; +const NUM_REG_FILES: usize = 6; impl RegFile { /// Returns true if the register file is uniform across a wave pub fn is_uniform(&self) -> bool { match self { - RegFile::GPR | RegFile::Pred | RegFile::Mem => false, + RegFile::GPR | RegFile::Pred | RegFile::Bar | RegFile::Mem => false, RegFile::UGPR | RegFile::UPred => true, } } @@ -94,14 +99,16 @@ impl RegFile { pub fn is_gpr(&self) -> bool { match self { RegFile::GPR | RegFile::UGPR => true, - RegFile::Pred | RegFile::UPred | RegFile::Mem => false, + RegFile::Pred | RegFile::UPred | RegFile::Bar | RegFile::Mem => { + false + } } } /// Returns true if the register file is a predicate register file pub fn is_predicate(&self) -> bool { match self { - RegFile::GPR | RegFile::UGPR | RegFile::Mem => false, + RegFile::GPR | RegFile::UGPR | RegFile::Bar | RegFile::Mem => false, RegFile::Pred | RegFile::UPred => true, } } @@ -136,6 +143,13 @@ impl RegFile { 0 } } + RegFile::Bar => { + if sm >= 70 { + 16 + } else { + 0 + } + } RegFile::Mem => 1 << 24, } } @@ -146,6 +160,7 @@ impl RegFile { RegFile::UGPR => "ur", RegFile::Pred => "p", RegFile::UPred => "up", + RegFile::Bar => "b", RegFile::Mem => "m", } } @@ -158,6 +173,7 @@ impl fmt::Display for RegFile { RegFile::UGPR => write!(f, "UGPR"), RegFile::Pred => write!(f, "Pred"), RegFile::UPred => write!(f, "UPred"), + RegFile::Bar => write!(f, "Bar"), RegFile::Mem => write!(f, "Mem"), } } @@ -178,7 +194,8 @@ impl TryFrom<u32> for RegFile { 1 => Ok(RegFile::UGPR), 2 => Ok(RegFile::Pred), 3 => Ok(RegFile::UPred), - 4 => Ok(RegFile::Mem), + 4 => Ok(RegFile::Bar), + 5 => Ok(RegFile::Mem), _ => Err("Invalid register file number"), } } @@ -299,6 +316,7 @@ impl<T> PerRegFile<T> { f(RegFile::UGPR), f(RegFile::Pred), f(RegFile::UPred), + f(RegFile::Bar), f(RegFile::Mem), ], } @@ -569,6 +587,7 @@ impl RegRef { RegFile::UGPR => 63, RegFile::Pred => 7, RegFile::UPred => 7, + RegFile::Bar => panic!("Bar has no zero index"), RegFile::Mem => panic!("Mem has no zero index"), } } @@ -786,6 +805,14 @@ impl SrcRef { } } + pub fn is_barrier(&self) -> bool { + match self { + SrcRef::SSA(ssa) => ssa.file() == RegFile::Bar, + SrcRef::Reg(reg) => reg.file() == RegFile::Bar, + _ => false, + } + } + pub fn as_reg(&self) -> Option<&RegRef> { match self { SrcRef::Reg(r) => Some(r), @@ -989,6 +1016,7 @@ pub enum SrcType { F64, I32, Pred, + Bar, } #[derive(Clone, Copy, PartialEq)] @@ -1161,6 +1189,7 @@ impl Src { self.src_ref.is_predicate() } + SrcType::Bar => self.src_mod.is_none() && self.src_ref.is_barrier(), } } } diff --git a/src/nouveau/compiler/nak_legalize.rs b/src/nouveau/compiler/nak_legalize.rs index 12cd51f5839..f8297249597 100644 --- a/src/nouveau/compiler/nak_legalize.rs +++ b/src/nouveau/compiler/nak_legalize.rs @@ -283,6 +283,7 @@ fn legalize_instr(b: &mut impl SSABuilder, instr: &mut Instr) { SrcType::Pred => { panic!("Predicates must be legalized explicitly"); } + SrcType::Bar => (), } } } diff --git a/src/nouveau/compiler/nak_opt_copy_prop.rs b/src/nouveau/compiler/nak_opt_copy_prop.rs index e3a34393675..5a80e783860 100644 --- a/src/nouveau/compiler/nak_opt_copy_prop.rs +++ b/src/nouveau/compiler/nak_opt_copy_prop.rs @@ -300,6 +300,7 @@ impl CopyPropPass { SrcType::F64 => { self.prop_to_f64_src(src); } + SrcType::Bar => (), } } diff --git a/src/nouveau/compiler/nak_opt_lop.rs b/src/nouveau/compiler/nak_opt_lop.rs index 2094799bdea..6192d0d54d6 100644 --- a/src/nouveau/compiler/nak_opt_lop.rs +++ b/src/nouveau/compiler/nak_opt_lop.rs @@ -170,7 +170,7 @@ impl LopPass { srcs[src_idx] = match ssa.file() { RegFile::GPR | RegFile::UGPR => SrcRef::Zero.into(), RegFile::Pred | RegFile::UPred => SrcRef::True.into(), - RegFile::Mem => panic!("Not a register"), + RegFile::Bar | RegFile::Mem => panic!("Not a normal register"), }; for i in 0..3 {
