Module: Mesa Branch: main Commit: 81eeb157f806de0232546c8a590051a58f1e0b3f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=81eeb157f806de0232546c8a590051a58f1e0b3f
Author: Samuel Pitoiset <samuel.pitoi...@gmail.com> Date: Thu Nov 16 16:54:30 2023 +0100 aco: export depth/stencil/samplemask in create_fs_jump_to_epilog() This currently has no effects because the store_output instructions are removed earlier (in ac_nir_lower_ps). Though, this will be needed for exporting MRTZ from PS epilogs for alpha to coverage on RDNA3. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413> --- src/amd/compiler/aco_instruction_selection.cpp | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index ae5a869568b..866d6de71f7 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -10928,7 +10928,19 @@ create_fs_jump_to_epilog(isel_context* ctx) { Builder bld(ctx->program, ctx->block); std::vector<Operand> exports; - PhysReg exports_start(256); /* VGPR 0 */ + unsigned vgpr = 256; /* VGPR 0 */ + + if (ctx->outputs.mask[FRAG_RESULT_DEPTH]) + exports.emplace_back(Operand(ctx->outputs.temps[FRAG_RESULT_DEPTH * 4u], PhysReg{vgpr++})); + + if (ctx->outputs.mask[FRAG_RESULT_STENCIL]) + exports.emplace_back(Operand(ctx->outputs.temps[FRAG_RESULT_STENCIL * 4u], PhysReg{vgpr++})); + + if (ctx->outputs.mask[FRAG_RESULT_SAMPLE_MASK]) + exports.emplace_back( + Operand(ctx->outputs.temps[FRAG_RESULT_SAMPLE_MASK * 4u], PhysReg{vgpr++})); + + PhysReg exports_start(vgpr); for (unsigned slot = FRAG_RESULT_DATA0; slot < FRAG_RESULT_DATA7 + 1; ++slot) { unsigned color_index = slot - FRAG_RESULT_DATA0;
