Module: Mesa Branch: main Commit: 9898c719a2ad1698cd4fe025bead6b185e783ba9 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9898c719a2ad1698cd4fe025bead6b185e783ba9
Author: José Roberto de Souza <jose.so...@intel.com> Date: Mon Dec 26 11:47:27 2022 -0800 intel/genxml/xe2: Update PIPE_CONTROL 'Tile Cache Flush Enable' and 'Generic Media State Clear' are now reserved bits in gfx20+. Signed-off-by: José Roberto de Souza <jose.so...@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26403> --- src/gallium/drivers/iris/iris_context.h | 2 +- src/gallium/drivers/iris/iris_state.c | 4 ++- src/intel/genxml/gen20.xml | 49 +++++++++++++++++++++++++++++++++ src/intel/vulkan/genX_cmd_buffer.c | 6 ++-- 4 files changed, 57 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h index 36491236d5a..74461c18eac 100644 --- a/src/gallium/drivers/iris/iris_context.h +++ b/src/gallium/drivers/iris/iris_context.h @@ -354,7 +354,7 @@ enum pipe_control_flags PIPE_CONTROL_STATE_CACHE_INVALIDATE = (1 << 22), PIPE_CONTROL_STALL_AT_SCOREBOARD = (1 << 23), PIPE_CONTROL_DEPTH_CACHE_FLUSH = (1 << 24), - PIPE_CONTROL_TILE_CACHE_FLUSH = (1 << 25), + PIPE_CONTROL_TILE_CACHE_FLUSH = (1 << 25), /* Not available in Gfx20+ */ PIPE_CONTROL_FLUSH_HDC = (1 << 26), PIPE_CONTROL_PSS_STALL_SYNC = (1 << 27), PIPE_CONTROL_L3_READ_ONLY_CACHE_INVALIDATE = (1 << 28), diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index a6ec245b473..a1c50143251 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -9603,7 +9603,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, #if GFX_VERx10 >= 125 pc.PSSStallSyncEnable = flags & PIPE_CONTROL_PSS_STALL_SYNC; #endif -#if GFX_VER >= 12 +#if GFX_VER == 12 pc.TileCacheFlushEnable = flags & PIPE_CONTROL_TILE_CACHE_FLUSH; #endif #if GFX_VER > 11 @@ -9628,7 +9628,9 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, flags & PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET; #endif pc.TLBInvalidate = flags & PIPE_CONTROL_TLB_INVALIDATE; +#if GFX_VERx10 < 200 pc.GenericMediaStateClear = flags & PIPE_CONTROL_MEDIA_STATE_CLEAR; +#endif pc.StallAtPixelScoreboard = flags & PIPE_CONTROL_STALL_AT_SCOREBOARD; pc.RenderTargetCacheFlushEnable = flags & PIPE_CONTROL_RENDER_TARGET_FLUSH; diff --git a/src/intel/genxml/gen20.xml b/src/intel/genxml/gen20.xml index 794233876be..d518aa68e94 100644 --- a/src/intel/genxml/gen20.xml +++ b/src/intel/genxml/gen20.xml @@ -299,4 +299,53 @@ <field name="Argument Buffer Start Address" start="130" end="191" type="address" /> <field name="COMPUTE_WALKER_BODY" start="192" end="1439" type="COMPUTE_WALKER_BODY" /> </instruction> + <instruction name="PIPE_CONTROL" bias="2" length="6" engine="render"> + <field name="DWord Length" start="0" end="7" type="uint" default="4" /> + <field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool" /> + <field name="L3 Read Only Cache Invalidation Enable" start="10" end="10" type="bool" /> + <field name="Untyped Data Port Cache Flush Enable" start="11" end="11" type="bool" /> + <field name="CCS Flush Enable" start="13" end="13" type="bool" /> + <field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0" /> + <field name="3D Command Opcode" start="24" end="26" type="uint" default="2" /> + <field name="Command SubType" start="27" end="28" type="uint" default="3" /> + <field name="Command Type" start="29" end="31" type="uint" default="3" /> + <field name="Depth Cache Flush Enable" start="32" end="32" type="bool" /> + <field name="Stall At Pixel Scoreboard" start="33" end="33" type="bool" /> + <field name="State Cache Invalidation Enable" start="34" end="34" type="bool" /> + <field name="Constant Cache Invalidation Enable" start="35" end="35" type="bool" /> + <field name="VF Cache Invalidation Enable" start="36" end="36" type="bool" /> + <field name="DC Flush Enable" start="37" end="37" type="bool" /> + <field name="Pipe Control Flush Enable" start="39" end="39" type="bool" /> + <field name="Notify Enable" start="40" end="40" type="bool" /> + <field name="Indirect State Pointers Disable" start="41" end="41" type="bool" /> + <field name="Texture Cache Invalidation Enable" start="42" end="42" type="bool" /> + <field name="Instruction Cache Invalidate Enable" start="43" end="43" type="bool" /> + <field name="Render Target Cache Flush Enable" start="44" end="44" type="bool" /> + <field name="Depth Stall Enable" start="45" end="45" type="bool" /> + <field name="Post Sync Operation" start="46" end="47" type="uint"> + <value name="No Write" value="0" /> + <value name="Write Immediate Data" value="1" /> + <value name="Write PS Depth Count" value="2" /> + <value name="Write Timestamp" value="3" /> + </field> + <field name="PSS Stall Sync Enable" start="49" end="49" type="bool" /> + <field name="TLB Invalidate" start="50" end="50" type="bool" /> + <field name="Depth Stall Sync Enable" start="51" end="51" type="bool" /> + <field name="Command Streamer Stall Enable" start="52" end="52" type="bool" /> + <field name="Store Data Index" start="53" end="53" type="uint" /> + <field name="Protected Memory Enable" start="54" end="54" type="bool" /> + <field name="LRI Post Sync Operation" start="55" end="55" type="uint"> + <value name="No LRI Operation" value="0" /> + <value name="MMIO Write Immediate Data" value="1" /> + </field> + <field name="Destination Address Type" start="56" end="56" type="uint" prefix="DAT"> + <value name="PPGTT" value="0" /> + <value name="GGTT" value="1" /> + </field> + <field name="Flush LLC" start="58" end="58" type="bool" /> + <field name="Protected Memory Disable" start="59" end="59" type="bool" /> + <field name="Command Cache Invalidate Enable" start="61" end="61" type="bool" /> + <field name="Address" start="66" end="111" type="address" /> + <field name="Immediate Data" start="128" end="191" type="uint" /> + </instruction> </genxml> diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 1266a7c80ec..eceb0e9f54f 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -60,8 +60,10 @@ convert_pc_to_bits(struct GENX(PIPE_CONTROL) *pc) { #if GFX_VERx10 >= 125 bits |= (pc->PSSStallSyncEnable) ? ANV_PIPE_PSS_STALL_SYNC_BIT : 0; #endif -#if GFX_VER >= 12 +#if GFX_VER == 12 bits |= (pc->TileCacheFlushEnable) ? ANV_PIPE_TILE_CACHE_FLUSH_BIT : 0; +#endif +#if GFX_VER >= 12 bits |= (pc->HDCPipelineFlushEnable) ? ANV_PIPE_HDC_PIPELINE_FLUSH_BIT : 0; #endif bits |= (pc->RenderTargetCacheFlushEnable) ? ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT : 0; @@ -2889,7 +2891,7 @@ genX(batch_emit_pipe_control_write)(struct anv_batch *batch, bits & ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT; pipe.CCSFlushEnable = bits & ANV_PIPE_CCS_CACHE_FLUSH_BIT; #endif -#if GFX_VER >= 12 +#if GFX_VER == 12 pipe.TileCacheFlushEnable = bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT; #endif #if GFX_VER > 11
