Module: Mesa Branch: main Commit: c4265536584eddef6aac1ce64fe69bcc6394de42 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c4265536584eddef6aac1ce64fe69bcc6394de42
Author: Sagar Ghuge <sagar.gh...@intel.com> Date: Wed Sep 27 16:40:02 2023 -0700 intel/compiler: Adjust assertion in lower_get_buffer_size() for Xe2 Signed-off-by: Sagar Ghuge <sagar.gh...@intel.com> Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Ian Romanick <ian.d.roman...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26639> --- src/intel/compiler/brw_lower_logical_sends.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp index 173fdf3e970..1a784010bf8 100644 --- a/src/intel/compiler/brw_lower_logical_sends.cpp +++ b/src/intel/compiler/brw_lower_logical_sends.cpp @@ -2996,7 +2996,7 @@ lower_get_buffer_size(const fs_builder &bld, fs_inst *inst) /* Since we can only execute this instruction on uniform bti/surface * handles, brw_fs_nir.cpp should already have limited this to SIMD8. */ - assert(inst->exec_size == 8); + assert(inst->exec_size == (devinfo->ver < 20 ? 8 : 16)); fs_reg surface = inst->src[GET_BUFFER_SIZE_SRC_SURFACE]; fs_reg surface_handle = inst->src[GET_BUFFER_SIZE_SRC_SURFACE_HANDLE];
