Module: Mesa Branch: main Commit: 78e45221bd271b7afc1c0eae3214001178d55247 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=78e45221bd271b7afc1c0eae3214001178d55247
Author: Samuel Pitoiset <samuel.pitoi...@gmail.com> Date: Thu Nov 30 10:43:21 2023 +0100 radv: emit the task shader in radv_emit_graphics_pipeline() It's a better place to do so. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26414> --- src/amd/vulkan/radv_cmd_buffer.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index adb10667497..6be6d1ca3c5 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1991,6 +1991,19 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer) radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.gs_copy_shader->bo); } + struct radv_shader *task_shader = cmd_buffer->state.shaders[MESA_SHADER_TASK]; + if (task_shader) { + radv_emit_compute_shader(device->physical_device, cmd_buffer->gang.cs, task_shader); + + /* Relocate the task shader because RGP requires shaders to be contiguous in memory. */ + if (pipeline->sqtt_shaders_reloc) { + const struct radv_sqtt_shaders_reloc *reloc = pipeline->sqtt_shaders_reloc; + const uint64_t va = reloc->va[MESA_SHADER_TASK]; + + radeon_set_sh_reg(cmd_buffer->gang.cs, R_00B830_COMPUTE_PGM_LO, va >> 8); + } + } + if (unlikely(cmd_buffer->device->trace_bo)) radv_save_pipeline(cmd_buffer, &pipeline->base); @@ -9039,7 +9052,6 @@ radv_before_taskmesh_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_ if (unlikely(!info->count)) return false; - struct radv_physical_device *pdevice = cmd_buffer->device->physical_device; struct radeon_cmdbuf *ace_cs = cmd_buffer->gang.cs; struct radv_shader *task_shader = cmd_buffer->state.shaders[MESA_SHADER_TASK]; @@ -9047,9 +9059,6 @@ radv_before_taskmesh_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_ const VkShaderStageFlags stages = VK_SHADER_STAGE_MESH_BIT_EXT | VK_SHADER_STAGE_FRAGMENT_BIT | (task_shader ? VK_SHADER_STAGE_TASK_BIT_EXT : 0); - const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; - const bool pipeline_is_dirty = - cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE && pipeline != cmd_buffer->state.emitted_graphics_pipeline; const bool need_task_semaphore = task_shader && radv_flush_gang_leader_semaphore(cmd_buffer); ASSERTED const unsigned cdw_max = @@ -9061,17 +9070,6 @@ radv_before_taskmesh_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_ radv_emit_fb_mip_change_flush(cmd_buffer); radv_emit_all_graphics_states(cmd_buffer, info); - if (task_shader && pipeline_is_dirty) { - radv_emit_compute_shader(pdevice, ace_cs, task_shader); - - /* Relocate the task shader because RGP requires shaders to be contiguous in memory. */ - if (pipeline->sqtt_shaders_reloc) { - const struct radv_sqtt_shaders_reloc *reloc = pipeline->sqtt_shaders_reloc; - const uint64_t va = reloc->va[MESA_SHADER_TASK]; - - radeon_set_sh_reg(ace_cs, R_00B830_COMPUTE_PGM_LO, va >> 8); - } - } si_emit_cache_flush(cmd_buffer);
