Module: Mesa Branch: main Commit: 2f25679b3fc18bd43a3cd327c12b92e5f666f529 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f25679b3fc18bd43a3cd327c12b92e5f666f529
Author: Tapani Pälli <tapani.pa...@intel.com> Date: Wed Dec 13 13:40:17 2023 +0200 anv: cleanup, use intel_needs_workaround instead of is_dg2 Signed-off-by: Tapani Pälli <tapani.pa...@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Reviewed-by: José Roberto de Souza <jose.so...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26666> --- src/intel/vulkan/genX_pipeline.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 68e7a3f2a7d..a0740b7c603 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -1918,16 +1918,16 @@ genX(graphics_pipeline_emit)(struct anv_graphics_pipeline *pipeline, #endif #if GFX_VERx10 >= 125 - struct anv_device *device = pipeline->base.base.device; anv_pipeline_emit(pipeline, partial.vfg, GENX(3DSTATE_VFG), vfg) { /* If 3DSTATE_TE: TE Enable == 1 then RR_STRICT else RR_FREE*/ vfg.DistributionMode = anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL) ? RR_STRICT : RR_FREE; vfg.DistributionGranularity = BatchLevelGranularity; - /* Wa_14014890652 */ - if (intel_device_info_is_dg2(device->info)) - vfg.GranularityThresholdDisable = 1; +#if INTEL_WA_14014851047_GFX_VER + vfg.GranularityThresholdDisable = + intel_needs_workaround(pipeline->base.base.device->info, 14014851047); +#endif /* 192 vertices for TRILIST_ADJ */ vfg.ListNBatchSizeScale = 0; /* Batch size of 384 vertices */
