Module: Mesa
Branch: main
Commit: f76f4be301ef311e6be21486b6a3f5fd5e90240f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f76f4be301ef311e6be21486b6a3f5fd5e90240f
Author: Dave Airlie <airl...@redhat.com>
Date: Mon Dec 18 16:47:56 2023 +1000
intel/compiler: move gen5 final pass to actually be final pass
This got broken by the register conversion, this pass needs to be
after all the others.
Fixes: ce75c3c3fea9 ("intel: Switch to intrinsic-based registers")
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26731>
---
src/intel/compiler/brw_nir.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 073193308a8..e0043fffebf 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -1757,14 +1757,6 @@ brw_postprocess_nir(nir_shader *nir, const struct
brw_compiler *compiler,
if (OPT(nir_opt_rematerialize_compares))
OPT(nir_opt_dce);
- /* This is the last pass we run before we start emitting stuff. It
- * determines when we need to insert boolean resolves on Gen <= 5. We
- * run it last because it stashes data in instr->pass_flags and we don't
- * want that to be squashed by other NIR passes.
- */
- if (devinfo->ver <= 5)
- brw_nir_analyze_boolean_resolves(nir);
-
OPT(nir_opt_dce);
/* The mesh stages require this pass to be called at the last minute,
@@ -1777,6 +1769,15 @@ brw_postprocess_nir(nir_shader *nir, const struct
brw_compiler *compiler,
brw_nir_adjust_payload(nir);
nir_trivialize_registers(nir);
+
+ /* This is the last pass we run before we start emitting stuff. It
+ * determines when we need to insert boolean resolves on Gen <= 5. We
+ * run it last because it stashes data in instr->pass_flags and we don't
+ * want that to be squashed by other NIR passes.
+ */
+ if (devinfo->ver <= 5)
+ brw_nir_analyze_boolean_resolves(nir);
+
nir_sweep(nir);
if (unlikely(debug_enabled)) {
