Module: Mesa Branch: main Commit: 188c349e51ea16c0e8c914405d31e14eea9f45c5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=188c349e51ea16c0e8c914405d31e14eea9f45c5
Author: Mark Janes <markja...@swizzler.org> Date: Sun Dec 31 11:00:05 2023 -0800 intel: remove workaround for preproduction DG2 steppings DG2_G10 was released with stepping C0. DG2_G11 was released with stepping B1. Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26845> --- src/intel/compiler/brw_nir_lower_shader_calls.c | 51 +------------------------ src/intel/vulkan/anv_device.c | 10 +---- 2 files changed, 2 insertions(+), 59 deletions(-) diff --git a/src/intel/compiler/brw_nir_lower_shader_calls.c b/src/intel/compiler/brw_nir_lower_shader_calls.c index 040c631d1b4..554d3e2b782 100644 --- a/src/intel/compiler/brw_nir_lower_shader_calls.c +++ b/src/intel/compiler/brw_nir_lower_shader_calls.c @@ -323,56 +323,7 @@ brw_nir_create_trivial_return_shader(const struct brw_compiler *compiler, ralloc_steal(mem_ctx, b->shader); nir_shader *nir = b->shader; - /* Workaround not needed on DG2-G10-C0+ & DG2-G11-B0+ */ - if ((compiler->devinfo->platform == INTEL_PLATFORM_DG2_G10 && - compiler->devinfo->revision < 8) || - (compiler->devinfo->platform == INTEL_PLATFORM_DG2_G11 && - compiler->devinfo->revision < 4)) { - /* Reserve scratch space at the start of the shader's per-thread scratch - * space for the return BINDLESS_SHADER_RECORD address and data payload. - * When a shader is called, the calling shader will write the return BSR - * address in this region of the callee's scratch space. - */ - nir->scratch_size = BRW_BTD_STACK_CALLEE_DATA_SIZE; - - nir_function_impl *impl = nir_shader_get_entrypoint(nir); - - b->cursor = nir_before_impl(impl); - - nir_def *shader_type = nir_load_btd_shader_type_intel(b); - - nir_def *is_intersection_shader = - nir_ieq_imm(b, shader_type, GEN_RT_BTD_SHADER_TYPE_INTERSECTION); - nir_def *is_anyhit_shader = - nir_ieq_imm(b, shader_type, GEN_RT_BTD_SHADER_TYPE_ANY_HIT); - - nir_def *needs_commit_or_continue = - nir_ior(b, is_intersection_shader, is_anyhit_shader); - - nir_push_if(b, needs_commit_or_continue); - { - struct brw_nir_rt_mem_hit_defs hit_in = {}; - brw_nir_rt_load_mem_hit(b, &hit_in, false /* committed */); - - nir_def *ray_op = - nir_bcsel(b, is_intersection_shader, - nir_imm_int(b, GEN_RT_TRACE_RAY_CONTINUE), - nir_imm_int(b, GEN_RT_TRACE_RAY_COMMIT)); - nir_def *ray_level = hit_in.bvh_level; - - nir_trace_ray_intel(b, - nir_load_btd_global_arg_addr_intel(b), - ray_level, ray_op, - .synchronous = false); - } - nir_push_else(b, NULL); - { - brw_nir_btd_return(b); - } - nir_pop_if(b, NULL); - } else { - NIR_PASS_V(nir, brw_nir_lower_shader_returns); - } + NIR_PASS_V(nir, brw_nir_lower_shader_returns); return nir; } diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 217ed018e89..e6104259ff2 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -1376,15 +1376,7 @@ get_properties(const struct anv_physical_device *pdevice, props->fragmentShadingRateWithConservativeRasterization = true; props->fragmentShadingRateWithFragmentShaderInterlock = true; props->fragmentShadingRateWithCustomSampleLocations = true; - - /* Fix in DG2_G10_C0 and DG2_G11_B0. Consider any other Sku as having - * the fix. - */ - props->fragmentShadingRateStrictMultiplyCombiner = - pdevice->info.platform == INTEL_PLATFORM_DG2_G10 ? - pdevice->info.revision >= 8 : - pdevice->info.platform == INTEL_PLATFORM_DG2_G11 ? - pdevice->info.revision >= 4 : true; + props->fragmentShadingRateStrictMultiplyCombiner = true; if (pdevice->info.has_coarse_pixel_primitive_and_cb) { props->minFragmentShadingRateAttachmentTexelSize = (VkExtent2D) { 8, 8 };
