Module: Mesa Branch: main Commit: 744cb98bc689225add12881ff59ce574afed8531 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=744cb98bc689225add12881ff59ce574afed8531
Author: Samuel Pitoiset <samuel.pitoi...@gmail.com> Date: Mon Sep 18 10:28:38 2023 +0200 radv: add support for version 2 of all descriptor binding commands Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26757> --- src/amd/vulkan/meta/radv_meta.c | 4 +- src/amd/vulkan/meta/radv_meta_astc_decode.c | 4 +- src/amd/vulkan/meta/radv_meta_blit.c | 5 +- src/amd/vulkan/meta/radv_meta_blit2d.c | 19 +-- src/amd/vulkan/meta/radv_meta_buffer.c | 9 +- src/amd/vulkan/meta/radv_meta_bufimage.c | 29 ++-- src/amd/vulkan/meta/radv_meta_clear.c | 22 ++-- src/amd/vulkan/meta/radv_meta_copy_vrs_htile.c | 5 +- src/amd/vulkan/meta/radv_meta_dcc_retile.c | 5 +- src/amd/vulkan/meta/radv_meta_etc_decode.c | 5 +- src/amd/vulkan/meta/radv_meta_resolve_cs.c | 9 +- src/amd/vulkan/meta/radv_meta_resolve_fs.c | 5 +- src/amd/vulkan/radv_acceleration_structure.c | 59 +++++---- src/amd/vulkan/radv_cmd_buffer.c | 167 ++++++++++++++++-------- src/amd/vulkan/radv_device_generated_commands.c | 5 +- src/amd/vulkan/radv_query.c | 5 +- 16 files changed, 215 insertions(+), 142 deletions(-) diff --git a/src/amd/vulkan/meta/radv_meta.c b/src/amd/vulkan/meta/radv_meta.c index d6e01efc99a..7277ae001a2 100644 --- a/src/amd/vulkan/meta/radv_meta.c +++ b/src/amd/vulkan/meta/radv_meta.c @@ -215,8 +215,8 @@ radv_meta_restore(const struct radv_meta_saved_state *state, struct radv_cmd_buf if (state->flags & RADV_META_SAVE_GRAPHICS_PIPELINE) stages |= VK_SHADER_STAGE_ALL_GRAPHICS; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), VK_NULL_HANDLE, stages, 0, MAX_PUSH_CONSTANTS_SIZE, - state->push_constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), VK_NULL_HANDLE, stages, 0, + MAX_PUSH_CONSTANTS_SIZE, state->push_constants); } if (state->flags & RADV_META_SAVE_RENDER) { diff --git a/src/amd/vulkan/meta/radv_meta_astc_decode.c b/src/amd/vulkan/meta/radv_meta_astc_decode.c index 3659336ef42..c069889e303 100644 --- a/src/amd/vulkan/meta/radv_meta_astc_decode.c +++ b/src/amd/vulkan/meta/radv_meta_astc_decode.c @@ -80,8 +80,8 @@ decode_astc(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_ivie bool is_3Dimage = (src_iview->image->vk.image_type == VK_IMAGE_TYPE_3D) ? true : false; int push_constants[5] = {offset->x / blk_w, offset->y / blk_h, extent->width + offset->x, extent->height + offset->y, is_3Dimage}; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.etc_decode.pipeline_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 20, push_constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.etc_decode.pipeline_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 20, push_constants); struct radv_dispatch_info info = { .blocks[0] = DIV_ROUND_UP(extent->width, blk_w * 2), diff --git a/src/amd/vulkan/meta/radv_meta_blit.c b/src/amd/vulkan/meta/radv_meta_blit.c index a9e494e563e..0f733fe8630 100644 --- a/src/amd/vulkan/meta/radv_meta_blit.c +++ b/src/amd/vulkan/meta/radv_meta_blit.c @@ -23,6 +23,7 @@ #include "nir/nir_builder.h" #include "radv_meta.h" +#include "vk_common_entrypoints.h" struct blit_region { VkOffset3D src_offset; @@ -207,8 +208,8 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image, src_offset_1[1] / (float)src_height, src_offset_0[2] / (float)src_depth, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.blit.pipeline_layout, - VK_SHADER_STAGE_VERTEX_BIT, 0, 20, vertex_push_constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.blit.pipeline_layout, + VK_SHADER_STAGE_VERTEX_BIT, 0, 20, vertex_push_constants); VkPipeline *pipeline = NULL; unsigned fs_key = 0; diff --git a/src/amd/vulkan/meta/radv_meta_blit2d.c b/src/amd/vulkan/meta/radv_meta_blit2d.c index d9d701c248f..ea973e47c9e 100644 --- a/src/amd/vulkan/meta/radv_meta_blit2d.c +++ b/src/amd/vulkan/meta/radv_meta_blit2d.c @@ -26,6 +26,7 @@ #include "nir/nir_builder.h" #include "radv_meta.h" +#include "vk_common_entrypoints.h" #include "vk_format.h" enum blit2d_src_type { @@ -117,16 +118,16 @@ blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER, .pTexelBufferView = (VkBufferView[]){radv_buffer_view_to_handle(&tmp->bview)}}}); - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), - device->meta_state.blit2d[log2_samples].p_layouts[src_type], VK_SHADER_STAGE_FRAGMENT_BIT, - 16, 4, &src_buf->pitch); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), + device->meta_state.blit2d[log2_samples].p_layouts[src_type], + VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4, &src_buf->pitch); } else { create_iview(cmd_buffer, src_img, &tmp->iview, depth_format, aspects); if (src_type == BLIT2D_SRC_TYPE_IMAGE_3D) - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), - device->meta_state.blit2d[log2_samples].p_layouts[src_type], - VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4, &src_img->layer); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), + device->meta_state.blit2d[log2_samples].p_layouts[src_type], + VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4, &src_img->layer); radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS, device->meta_state.blit2d[log2_samples].p_layouts[src_type], 0, /* set */ @@ -224,9 +225,9 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer, struct radv_meta rects[r].src_y + rects[r].height, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), - device->meta_state.blit2d[log2_samples].p_layouts[src_type], VK_SHADER_STAGE_VERTEX_BIT, - 0, 16, vertex_push_constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), + device->meta_state.blit2d[log2_samples].p_layouts[src_type], + VK_SHADER_STAGE_VERTEX_BIT, 0, 16, vertex_push_constants); if (aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT || aspect_mask == VK_IMAGE_ASPECT_PLANE_0_BIT || aspect_mask == VK_IMAGE_ASPECT_PLANE_1_BIT || aspect_mask == VK_IMAGE_ASPECT_PLANE_2_BIT) { diff --git a/src/amd/vulkan/meta/radv_meta_buffer.c b/src/amd/vulkan/meta/radv_meta_buffer.c index fccf7ace12e..79aa49bf78b 100644 --- a/src/amd/vulkan/meta/radv_meta_buffer.c +++ b/src/amd/vulkan/meta/radv_meta_buffer.c @@ -4,6 +4,7 @@ #include "radv_cs.h" #include "sid.h" +#include "vk_common_entrypoints.h" static nir_shader * build_buffer_fill_shader(struct radv_device *dev) @@ -172,8 +173,8 @@ fill_buffer_shader(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t siz .data = data, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.buffer.fill_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(fill_consts), &fill_consts); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.buffer.fill_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(fill_consts), &fill_consts); radv_unaligned_dispatch(cmd_buffer, DIV_ROUND_UP(size, 16), 1, 1); @@ -199,8 +200,8 @@ copy_buffer_shader(struct radv_cmd_buffer *cmd_buffer, uint64_t src_va, uint64_t .max_offset = size - 16, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.buffer.copy_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(copy_consts), ©_consts); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.buffer.copy_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(copy_consts), ©_consts); radv_unaligned_dispatch(cmd_buffer, DIV_ROUND_UP(size, 16), 1, 1); diff --git a/src/amd/vulkan/meta/radv_meta_bufimage.c b/src/amd/vulkan/meta/radv_meta_bufimage.c index 12cc651cd5d..743b405507b 100644 --- a/src/amd/vulkan/meta/radv_meta_bufimage.c +++ b/src/amd/vulkan/meta/radv_meta_bufimage.c @@ -23,6 +23,7 @@ */ #include "nir/nir_builder.h" #include "radv_meta.h" +#include "vk_common_entrypoints.h" /* * GFX queue: Compute shader implementation of image->buffer copy @@ -1304,8 +1305,8 @@ radv_meta_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_b for (unsigned r = 0; r < num_rects; ++r) { unsigned push_constants[4] = {rects[r].src_x, rects[r].src_y, src->layer, dst->pitch}; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.itob.img_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.itob.img_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants); radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1); fixup_gfx9_cs_copy(cmd_buffer, dst, src, &rects[r], false); @@ -1376,8 +1377,8 @@ radv_meta_buffer_to_image_cs_r32g32b32(struct radv_cmd_buffer *cmd_buffer, struc src->pitch, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.btoi_r32g32b32.img_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.btoi_r32g32b32.img_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants); radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1); } @@ -1447,8 +1448,8 @@ radv_meta_buffer_to_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_met dst->layer, src->pitch, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.btoi.img_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.btoi.img_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants); radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1); fixup_gfx9_cs_copy(cmd_buffer, src, dst, &rects[r], true); @@ -1521,8 +1522,8 @@ radv_meta_image_to_image_cs_r32g32b32(struct radv_cmd_buffer *cmd_buffer, struct unsigned push_constants[6] = { rects[r].src_x, rects[r].src_y, src_stride, rects[r].dst_x, rects[r].dst_y, dst_stride, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.itoi_r32g32b32.img_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 24, push_constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.itoi_r32g32b32.img_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 24, push_constants); radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1); } @@ -1605,8 +1606,8 @@ radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta unsigned push_constants[6] = { rects[r].src_x, rects[r].src_y, src->layer, rects[r].dst_x, rects[r].dst_y, dst->layer, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.itoi.img_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 24, push_constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.itoi.img_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 24, push_constants); radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1); } @@ -1664,8 +1665,8 @@ radv_meta_clear_image_cs_r32g32b32(struct radv_cmd_buffer *cmd_buffer, struct ra stride, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.cleari_r32g32b32.img_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.cleari_r32g32b32.img_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants); radv_unaligned_dispatch(cmd_buffer, dst->image->vk.extent.width, dst->image->vk.extent.height, 1); @@ -1726,8 +1727,8 @@ radv_meta_clear_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_bl clear_color->uint32[0], clear_color->uint32[1], clear_color->uint32[2], clear_color->uint32[3], dst->layer, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.cleari.img_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 20, push_constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.cleari.img_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 20, push_constants); radv_unaligned_dispatch(cmd_buffer, dst->image->vk.extent.width, dst->image->vk.extent.height, 1); diff --git a/src/amd/vulkan/meta/radv_meta_clear.c b/src/amd/vulkan/meta/radv_meta_clear.c index 67b8667818d..b10cfa8f74b 100644 --- a/src/amd/vulkan/meta/radv_meta_clear.c +++ b/src/amd/vulkan/meta/radv_meta_clear.c @@ -338,8 +338,8 @@ emit_color_clear(struct radv_cmd_buffer *cmd_buffer, const VkClearAttachment *cl assert(samples_log2 < ARRAY_SIZE(device->meta_state.color_clear)); assert(pipeline); - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.clear_color_p_layout, - VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16, &clear_value); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.clear_color_p_layout, + VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16, &clear_value); radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline); @@ -548,11 +548,12 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer, VkClearDepthStencilV clear_value.depth = 1.0f; if (cmd_buffer->device->vk.enabled_extensions.EXT_depth_range_unrestricted) { - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.clear_depth_unrestricted_p_layout, - VK_SHADER_STAGE_FRAGMENT_BIT, 0, 4, &clear_value.depth); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), + device->meta_state.clear_depth_unrestricted_p_layout, VK_SHADER_STAGE_FRAGMENT_BIT, 0, + 4, &clear_value.depth); } else { - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.clear_depth_p_layout, - VK_SHADER_STAGE_VERTEX_BIT, 0, 4, &clear_value.depth); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.clear_depth_p_layout, + VK_SHADER_STAGE_VERTEX_BIT, 0, 4, &clear_value.depth); } uint32_t prev_reference = cmd_buffer->state.dynamic.vk.ds.stencil.front.reference; @@ -626,8 +627,8 @@ clear_htile_mask(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im ~htile_mask, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), state->clear_htile_mask_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 8, constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), state->clear_htile_mask_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 8, constants); vk_common_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 1); @@ -1312,8 +1313,9 @@ radv_clear_dcc_comp_to_single(struct radv_cmd_buffer *cmd_buffer, struct radv_im color_values[3], }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.clear_dcc_comp_to_single_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 24, constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), + device->meta_state.clear_dcc_comp_to_single_p_layout, VK_SHADER_STAGE_COMPUTE_BIT, 0, + 24, constants); radv_unaligned_dispatch(cmd_buffer, dcc_width, dcc_height, layer_count); diff --git a/src/amd/vulkan/meta/radv_meta_copy_vrs_htile.c b/src/amd/vulkan/meta/radv_meta_copy_vrs_htile.c index 02b3be7de01..bf1e6ccd7d4 100644 --- a/src/amd/vulkan/meta/radv_meta_copy_vrs_htile.c +++ b/src/amd/vulkan/meta/radv_meta_copy_vrs_htile.c @@ -26,6 +26,7 @@ #include "radv_meta.h" #include "radv_private.h" +#include "vk_common_entrypoints.h" #include "vk_format.h" void @@ -263,8 +264,8 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_i read_htile_value, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), state->copy_vrs_htile_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 20, constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), state->copy_vrs_htile_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 20, constants); uint32_t width = DIV_ROUND_UP(rect->extent.width, 8); uint32_t height = DIV_ROUND_UP(rect->extent.height, 8); diff --git a/src/amd/vulkan/meta/radv_meta_dcc_retile.c b/src/amd/vulkan/meta/radv_meta_dcc_retile.c index 9523fe76fea..dd2389793b4 100644 --- a/src/amd/vulkan/meta/radv_meta_dcc_retile.c +++ b/src/amd/vulkan/meta/radv_meta_dcc_retile.c @@ -26,6 +26,7 @@ #include "radv_meta.h" #include "radv_private.h" +#include "vk_common_entrypoints.h" static nir_shader * build_dcc_retile_compute_shader(struct radv_device *dev, struct radeon_surf *surf) @@ -255,8 +256,8 @@ radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image) image->planes[0].surface.u.gfx9.color.display_dcc_pitch_max + 1, image->planes[0].surface.u.gfx9.color.display_dcc_height, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.dcc_retile.p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.dcc_retile.p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, constants); radv_unaligned_dispatch(cmd_buffer, dcc_width, dcc_height, 1); diff --git a/src/amd/vulkan/meta/radv_meta_etc_decode.c b/src/amd/vulkan/meta/radv_meta_etc_decode.c index 9089af725f2..28b3c907682 100644 --- a/src/amd/vulkan/meta/radv_meta_etc_decode.c +++ b/src/amd/vulkan/meta/radv_meta_etc_decode.c @@ -28,6 +28,7 @@ #include "radv_meta.h" #include "radv_private.h" #include "sid.h" +#include "vk_common_entrypoints.h" #include "vk_format.h" VkResult @@ -112,8 +113,8 @@ decode_etc(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_iview offset->x, offset->y, offset->z, src_iview->image->vk.format, src_iview->image->vk.image_type, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.etc_decode.pipeline_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 20, push_constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.etc_decode.pipeline_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 20, push_constants); radv_unaligned_dispatch(cmd_buffer, extent->width, extent->height, extent->depth); } diff --git a/src/amd/vulkan/meta/radv_meta_resolve_cs.c b/src/amd/vulkan/meta/radv_meta_resolve_cs.c index 423d0f5326d..0b7b3490061 100644 --- a/src/amd/vulkan/meta/radv_meta_resolve_cs.c +++ b/src/amd/vulkan/meta/radv_meta_resolve_cs.c @@ -30,6 +30,7 @@ #include "radv_meta.h" #include "radv_private.h" #include "sid.h" +#include "vk_common_entrypoints.h" #include "vk_format.h" static nir_def * @@ -484,8 +485,8 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_ivi dst_offset->x, dst_offset->y, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.resolve_compute.p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.resolve_compute.p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants); radv_unaligned_dispatch(cmd_buffer, resolve_extent->width, resolve_extent->height, 1); } @@ -569,8 +570,8 @@ emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image uint32_t push_constants[2] = {resolve_offset->x, resolve_offset->y}; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.resolve_compute.p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(push_constants), push_constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.resolve_compute.p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(push_constants), push_constants); radv_unaligned_dispatch(cmd_buffer, resolve_extent->width, resolve_extent->height, resolve_extent->depth); } diff --git a/src/amd/vulkan/meta/radv_meta_resolve_fs.c b/src/amd/vulkan/meta/radv_meta_resolve_fs.c index ef6cae13a21..572828fb641 100644 --- a/src/amd/vulkan/meta/radv_meta_resolve_fs.c +++ b/src/amd/vulkan/meta/radv_meta_resolve_fs.c @@ -28,6 +28,7 @@ #include "radv_meta.h" #include "radv_private.h" #include "sid.h" +#include "vk_common_entrypoints.h" #include "vk_format.h" static nir_shader * @@ -613,8 +614,8 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_ivi src_offset->x - dst_offset->x, src_offset->y - dst_offset->y, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.resolve_fragment.p_layout, - VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8, push_constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.resolve_fragment.p_layout, + VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8, push_constants); pipeline = radv_get_resolve_pipeline(cmd_buffer, src_iview, dst_iview); diff --git a/src/amd/vulkan/radv_acceleration_structure.c b/src/amd/vulkan/radv_acceleration_structure.c index 10f461956f6..3a9bf553208 100644 --- a/src/amd/vulkan/radv_acceleration_structure.c +++ b/src/amd/vulkan/radv_acceleration_structure.c @@ -696,8 +696,8 @@ build_leaves(VkCommandBuffer commandBuffer, uint32_t infoCount, unreachable("Unknown geometryType"); } - radv_CmdPushConstants(commandBuffer, cmd_buffer->device->meta_state.accel_struct_build.leaf_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(leaf_consts), &leaf_consts); + vk_common_CmdPushConstants(commandBuffer, cmd_buffer->device->meta_state.accel_struct_build.leaf_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(leaf_consts), &leaf_consts); radv_unaligned_dispatch(cmd_buffer, buildRangeInfo->primitiveCount, 1, 1); bvh_states[i].leaf_node_count += buildRangeInfo->primitiveCount; @@ -724,8 +724,8 @@ morton_generate(VkCommandBuffer commandBuffer, uint32_t infoCount, .ids = pInfos[i].scratchData.deviceAddress + bvh_states[i].scratch.sort_buffer_offset[0], }; - radv_CmdPushConstants(commandBuffer, cmd_buffer->device->meta_state.accel_struct_build.morton_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(consts), &consts); + vk_common_CmdPushConstants(commandBuffer, cmd_buffer->device->meta_state.accel_struct_build.morton_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(consts), &consts); radv_unaligned_dispatch(cmd_buffer, bvh_states[i].node_count, 1, 1); } @@ -860,8 +860,8 @@ morton_sort(VkCommandBuffer commandBuffer, uint32_t infoCount, .passes = passes, }; - radv_CmdPushConstants(commandBuffer, rs->pipeline_layouts.named.histogram, VK_SHADER_STAGE_COMPUTE_BIT, 0, - sizeof(push_histogram), &push_histogram); + vk_common_CmdPushConstants(commandBuffer, rs->pipeline_layouts.named.histogram, VK_SHADER_STAGE_COMPUTE_BIT, 0, + sizeof(push_histogram), &push_histogram); vk_common_CmdDispatch(commandBuffer, bvh_states[i].histo_blocks, 1, 1); } @@ -885,8 +885,8 @@ morton_sort(VkCommandBuffer commandBuffer, uint32_t infoCount, .devaddr_histograms = internal_addr + rs->internal.histograms.offset, }; - radv_CmdPushConstants(commandBuffer, rs->pipeline_layouts.named.prefix, VK_SHADER_STAGE_COMPUTE_BIT, 0, - sizeof(push_prefix), &push_prefix); + vk_common_CmdPushConstants(commandBuffer, rs->pipeline_layouts.named.prefix, VK_SHADER_STAGE_COMPUTE_BIT, 0, + sizeof(push_prefix), &push_prefix); vk_common_CmdDispatch(commandBuffer, passes, 1, 1); } @@ -929,8 +929,8 @@ morton_sort(VkCommandBuffer commandBuffer, uint32_t infoCount, bvh_states[i].push_scatter.pass_offset = (pass_idx & 3) * RS_RADIX_LOG2; - radv_CmdPushConstants(commandBuffer, pl, VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(struct rs_push_scatter), - &bvh_states[i].push_scatter); + vk_common_CmdPushConstants(commandBuffer, pl, VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(struct rs_push_scatter), + &bvh_states[i].push_scatter); vk_common_CmdDispatch(commandBuffer, bvh_states[i].scatter_blocks, 1, 1); @@ -972,8 +972,8 @@ lbvh_build_internal(VkCommandBuffer commandBuffer, uint32_t infoCount, .internal_node_base = bvh_states[i].scratch.internal_node_offset - bvh_states[i].scratch.ir_offset, }; - radv_CmdPushConstants(commandBuffer, cmd_buffer->device->meta_state.accel_struct_build.lbvh_main_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(consts), &consts); + vk_common_CmdPushConstants(commandBuffer, cmd_buffer->device->meta_state.accel_struct_build.lbvh_main_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(consts), &consts); radv_unaligned_dispatch(cmd_buffer, internal_node_count, 1, 1); bvh_states[i].node_count = internal_node_count; bvh_states[i].internal_node_count = internal_node_count; @@ -995,8 +995,9 @@ lbvh_build_internal(VkCommandBuffer commandBuffer, uint32_t infoCount, .internal_node_base = bvh_states[i].scratch.internal_node_offset - bvh_states[i].scratch.ir_offset, }; - radv_CmdPushConstants(commandBuffer, cmd_buffer->device->meta_state.accel_struct_build.lbvh_generate_ir_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(consts), &consts); + vk_common_CmdPushConstants(commandBuffer, + cmd_buffer->device->meta_state.accel_struct_build.lbvh_generate_ir_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(consts), &consts); radv_unaligned_dispatch(cmd_buffer, bvh_states[i].internal_node_count, 1, 1); } } @@ -1032,8 +1033,8 @@ ploc_build_internal(VkCommandBuffer commandBuffer, uint32_t infoCount, .internal_node_offset = bvh_states[i].scratch.internal_node_offset - bvh_states[i].scratch.ir_offset, }; - radv_CmdPushConstants(commandBuffer, cmd_buffer->device->meta_state.accel_struct_build.ploc_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(consts), &consts); + vk_common_CmdPushConstants(commandBuffer, cmd_buffer->device->meta_state.accel_struct_build.ploc_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(consts), &consts); vk_common_CmdDispatch(commandBuffer, MAX2(DIV_ROUND_UP(bvh_states[i].node_count, PLOC_WORKGROUP_SIZE), 1), 1, 1); } } @@ -1078,8 +1079,8 @@ encode_nodes(VkCommandBuffer commandBuffer, uint32_t infoCount, .leaf_node_count = bvh_states[i].leaf_node_count, .geometry_type = geometry_type, }; - radv_CmdPushConstants(commandBuffer, cmd_buffer->device->meta_state.accel_struct_build.encode_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(args), &args); + vk_common_CmdPushConstants(commandBuffer, cmd_buffer->device->meta_state.accel_struct_build.encode_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(args), &args); struct radv_dispatch_info dispatch = { .unaligned = true, @@ -1118,8 +1119,8 @@ init_header(VkCommandBuffer commandBuffer, uint32_t infoCount, .instance_count = instance_count, }; - radv_CmdPushConstants(commandBuffer, cmd_buffer->device->meta_state.accel_struct_build.header_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(args), &args); + vk_common_CmdPushConstants(commandBuffer, cmd_buffer->device->meta_state.accel_struct_build.header_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(args), &args); radv_unaligned_dispatch(cmd_buffer, 1, 1, 1); } @@ -1287,9 +1288,9 @@ radv_CmdCopyAccelerationStructureKHR(VkCommandBuffer commandBuffer, const VkCopy .mode = RADV_COPY_MODE_COPY, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), - cmd_buffer->device->meta_state.accel_struct_build.copy_p_layout, VK_SHADER_STAGE_COMPUTE_BIT, - 0, sizeof(consts), &consts); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), + cmd_buffer->device->meta_state.accel_struct_build.copy_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(consts), &consts); cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT, NULL); @@ -1354,9 +1355,9 @@ radv_CmdCopyMemoryToAccelerationStructureKHR(VkCommandBuffer commandBuffer, .mode = RADV_COPY_MODE_DESERIALIZE, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), - cmd_buffer->device->meta_state.accel_struct_build.copy_p_layout, VK_SHADER_STAGE_COMPUTE_BIT, - 0, sizeof(consts), &consts); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), + cmd_buffer->device->meta_state.accel_struct_build.copy_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(consts), &consts); vk_common_CmdDispatch(commandBuffer, 512, 1, 1); radv_meta_restore(&saved_state, cmd_buffer); @@ -1389,9 +1390,9 @@ radv_CmdCopyAccelerationStructureToMemoryKHR(VkCommandBuffer commandBuffer, .mode = RADV_COPY_MODE_SERIALIZE, }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), - cmd_buffer->device->meta_state.accel_struct_build.copy_p_layout, VK_SHADER_STAGE_COMPUTE_BIT, - 0, sizeof(consts), &consts); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), + cmd_buffer->device->meta_state.accel_struct_build.copy_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(consts), &consts); cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT, NULL); diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 259f3786cfb..c11d75cf337 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -5949,22 +5949,18 @@ radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoint radv_cs_add_buffer(ws, cmd_buffer->cs, set->header.bo); } -VKAPI_ATTR void VKAPI_CALL -radv_CmdBindDescriptorSets(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, - VkPipelineLayout _layout, uint32_t firstSet, uint32_t descriptorSetCount, - const VkDescriptorSet *pDescriptorSets, uint32_t dynamicOffsetCount, - const uint32_t *pDynamicOffsets) +static void +radv_bind_descriptor_sets(struct radv_cmd_buffer *cmd_buffer, + const VkBindDescriptorSetsInfoKHR *pBindDescriptorSetsInfo, VkPipelineBindPoint bind_point) { - RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); - RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout); - unsigned dyn_idx = 0; - + RADV_FROM_HANDLE(radv_pipeline_layout, layout, pBindDescriptorSetsInfo->layout); const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS; - struct radv_descriptor_state *descriptors_state = radv_get_descriptors_state(cmd_buffer, pipelineBindPoint); + struct radv_descriptor_state *descriptors_state = radv_get_descriptors_state(cmd_buffer, bind_point); + unsigned dyn_idx = 0; - for (unsigned i = 0; i < descriptorSetCount; ++i) { - unsigned set_idx = i + firstSet; - RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]); + for (unsigned i = 0; i < pBindDescriptorSetsInfo->descriptorSetCount; ++i) { + unsigned set_idx = i + pBindDescriptorSetsInfo->firstSet; + RADV_FROM_HANDLE(radv_descriptor_set, set, pBindDescriptorSetsInfo->pDescriptorSets[i]); if (!set) continue; @@ -5972,20 +5968,20 @@ radv_CmdBindDescriptorSets(VkCommandBuffer commandBuffer, VkPipelineBindPoint pi /* If the set is already bound we only need to update the * (potentially changed) dynamic offsets. */ if (descriptors_state->sets[set_idx] != set || !(descriptors_state->valid & (1u << set_idx))) { - radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, set_idx); + radv_bind_descriptor_set(cmd_buffer, bind_point, set, set_idx); } for (unsigned j = 0; j < set->header.layout->dynamic_offset_count; ++j, ++dyn_idx) { - unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start; + unsigned idx = j + layout->set[i + pBindDescriptorSetsInfo->firstSet].dynamic_offset_start; uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4; - assert(dyn_idx < dynamicOffsetCount); + assert(dyn_idx < pBindDescriptorSetsInfo->dynamicOffsetCount); struct radv_descriptor_range *range = set->header.dynamic_descriptors + j; if (!range->va) { memset(dst, 0, 4 * 4); } else { - uint64_t va = range->va + pDynamicOffsets[dyn_idx]; + uint64_t va = range->va + pBindDescriptorSetsInfo->pDynamicOffsets[dyn_idx]; dst[0] = va; dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32); dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size; @@ -6008,6 +6004,25 @@ radv_CmdBindDescriptorSets(VkCommandBuffer commandBuffer, VkPipelineBindPoint pi } } +VKAPI_ATTR void VKAPI_CALL +radv_CmdBindDescriptorSets2KHR(VkCommandBuffer commandBuffer, + const VkBindDescriptorSetsInfoKHR *pBindDescriptorSetsInfo) +{ + RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); + + if (pBindDescriptorSetsInfo->stageFlags & VK_SHADER_STAGE_COMPUTE_BIT) { + radv_bind_descriptor_sets(cmd_buffer, pBindDescriptorSetsInfo, VK_PIPELINE_BIND_POINT_COMPUTE); + } + + if (pBindDescriptorSetsInfo->stageFlags & RADV_GRAPHICS_STAGE_BITS) { + radv_bind_descriptor_sets(cmd_buffer, pBindDescriptorSetsInfo, VK_PIPELINE_BIND_POINT_GRAPHICS); + } + + if (pBindDescriptorSetsInfo->stageFlags & RADV_RT_STAGE_BITS) { + radv_bind_descriptor_sets(cmd_buffer, pBindDescriptorSetsInfo, VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR); + } +} + static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer, struct radv_descriptor_set *set, struct radv_descriptor_set_layout *layout, VkPipelineBindPoint bind_point) @@ -6070,68 +6085,90 @@ radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer, VkPipelineBind radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set); } -VKAPI_ATTR void VKAPI_CALL -radv_CmdPushDescriptorSetKHR(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, - VkPipelineLayout _layout, uint32_t set, uint32_t descriptorWriteCount, - const VkWriteDescriptorSet *pDescriptorWrites) +static void +radv_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer, const VkPushDescriptorSetInfoKHR *pPushDescriptorSetInfo, + VkPipelineBindPoint bind_point) { - RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); - RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout); - struct radv_descriptor_state *descriptors_state = radv_get_descriptors_state(cmd_buffer, pipelineBindPoint); + RADV_FROM_HANDLE(radv_pipeline_layout, layout, pPushDescriptorSetInfo->layout); + struct radv_descriptor_state *descriptors_state = radv_get_descriptors_state(cmd_buffer, bind_point); struct radv_descriptor_set *push_set = (struct radv_descriptor_set *)&descriptors_state->push_set.set; - assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR); + assert(layout->set[pPushDescriptorSetInfo->set].layout->flags & + VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR); - if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout, pipelineBindPoint)) + if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[pPushDescriptorSetInfo->set].layout, + bind_point)) return; /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR() * because it is invalid, according to Vulkan spec. */ - for (int i = 0; i < descriptorWriteCount; i++) { - ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i]; + for (int i = 0; i < pPushDescriptorSetInfo->descriptorWriteCount; i++) { + ASSERTED const VkWriteDescriptorSet *writeset = &pPushDescriptorSetInfo->pDescriptorWrites[i]; assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK); } radv_cmd_update_descriptor_sets(cmd_buffer->device, cmd_buffer, radv_descriptor_set_to_handle(push_set), - descriptorWriteCount, pDescriptorWrites, 0, NULL); + pPushDescriptorSetInfo->descriptorWriteCount, + pPushDescriptorSetInfo->pDescriptorWrites, 0, NULL); - radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set); + radv_set_descriptor_set(cmd_buffer, bind_point, push_set, pPushDescriptorSetInfo->set); radv_flush_push_descriptors(cmd_buffer, descriptors_state); } VKAPI_ATTR void VKAPI_CALL -radv_CmdPushDescriptorSetWithTemplateKHR(VkCommandBuffer commandBuffer, - VkDescriptorUpdateTemplate descriptorUpdateTemplate, VkPipelineLayout _layout, - uint32_t set, const void *pData) +radv_CmdPushDescriptorSet2KHR(VkCommandBuffer commandBuffer, const VkPushDescriptorSetInfoKHR *pPushDescriptorSetInfo) { RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); - RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout); - RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate); + + if (pPushDescriptorSetInfo->stageFlags & VK_SHADER_STAGE_COMPUTE_BIT) { + radv_push_descriptor_set(cmd_buffer, pPushDescriptorSetInfo, VK_PIPELINE_BIND_POINT_COMPUTE); + } + + if (pPushDescriptorSetInfo->stageFlags & RADV_GRAPHICS_STAGE_BITS) { + radv_push_descriptor_set(cmd_buffer, pPushDescriptorSetInfo, VK_PIPELINE_BIND_POINT_GRAPHICS); + } + + if (pPushDescriptorSetInfo->stageFlags & RADV_RT_STAGE_BITS) { + radv_push_descriptor_set(cmd_buffer, pPushDescriptorSetInfo, VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR); + } +} + +VKAPI_ATTR void VKAPI_CALL +radv_CmdPushDescriptorSetWithTemplate2KHR( + VkCommandBuffer commandBuffer, const VkPushDescriptorSetWithTemplateInfoKHR *pPushDescriptorSetWithTemplateInfo) +{ + RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); + RADV_FROM_HANDLE(radv_pipeline_layout, layout, pPushDescriptorSetWithTemplateInfo->layout); + RADV_FROM_HANDLE(radv_descriptor_update_template, templ, + pPushDescriptorSetWithTemplateInfo->descriptorUpdateTemplate); struct radv_descriptor_state *descriptors_state = radv_get_descriptors_state(cmd_buffer, templ->bind_point); struct radv_descriptor_set *push_set = (struct radv_descriptor_set *)&descriptors_state->push_set.set; - assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR); + assert(layout->set[pPushDescriptorSetWithTemplateInfo->set].layout->flags & + VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR); - if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout, templ->bind_point)) + if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[pPushDescriptorSetWithTemplateInfo->set].layout, + templ->bind_point)) return; - radv_cmd_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set, descriptorUpdateTemplate, - pData); + radv_cmd_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set, + pPushDescriptorSetWithTemplateInfo->descriptorUpdateTemplate, + pPushDescriptorSetWithTemplateInfo->pData); - radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set); + radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, pPushDescriptorSetWithTemplateInfo->set); radv_flush_push_descriptors(cmd_buffer, descriptors_state); } VKAPI_ATTR void VKAPI_CALL -radv_CmdPushConstants(VkCommandBuffer commandBuffer, VkPipelineLayout layout, VkShaderStageFlags stageFlags, - uint32_t offset, uint32_t size, const void *pValues) +radv_CmdPushConstants2KHR(VkCommandBuffer commandBuffer, const VkPushConstantsInfoKHR *pPushConstantsInfo) { RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); - memcpy(cmd_buffer->push_constants + offset, pValues, size); - cmd_buffer->push_constant_stages |= stageFlags; + memcpy(cmd_buffer->push_constants + pPushConstantsInfo->offset, pPushConstantsInfo->pValues, + pPushConstantsInfo->size); + cmd_buffer->push_constant_stages |= pPushConstantsInfo->stageFlags; } VKAPI_ATTR VkResult VKAPI_CALL @@ -11192,26 +11229,48 @@ radv_CmdBindDescriptorBuffersEXT(VkCommandBuffer commandBuffer, uint32_t bufferC } } +static void +radv_set_descriptor_buffer_offsets(struct radv_cmd_buffer *cmd_buffer, + const VkSetDescriptorBufferOffsetsInfoEXT *pSetDescriptorBufferOffsetsInfo, + VkPipelineBindPoint bind_point) +{ + struct radv_descriptor_state *descriptors_state = radv_get_descriptors_state(cmd_buffer, bind_point); + + for (unsigned i = 0; i < pSetDescriptorBufferOffsetsInfo->setCount; i++) { + const uint32_t buffer_idx = pSetDescriptorBufferOffsetsInfo->pBufferIndices[i]; + const uint64_t offset = pSetDescriptorBufferOffsetsInfo->pOffsets[i]; + unsigned idx = i + pSetDescriptorBufferOffsetsInfo->firstSet; + + descriptors_state->descriptor_buffers[idx] = cmd_buffer->descriptor_buffers[buffer_idx] + offset; + + radv_set_descriptor_set(cmd_buffer, bind_point, NULL, idx); + } +} + VKAPI_ATTR void VKAPI_CALL -radv_CmdSetDescriptorBufferOffsetsEXT(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, - VkPipelineLayout _layout, uint32_t firstSet, uint32_t setCount, - const uint32_t *pBufferIndices, const VkDeviceSize *pOffsets) +radv_CmdSetDescriptorBufferOffsets2EXT(VkCommandBuffer commandBuffer, + const VkSetDescriptorBufferOffsetsInfoEXT *pSetDescriptorBufferOffsetsInfo) { RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); - struct radv_descriptor_state *descriptors_state = radv_get_descriptors_state(cmd_buffer, pipelineBindPoint); - for (unsigned i = 0; i < setCount; i++) { - unsigned idx = i + firstSet; + if (pSetDescriptorBufferOffsetsInfo->stageFlags & VK_SHADER_STAGE_COMPUTE_BIT) { + radv_set_descriptor_buffer_offsets(cmd_buffer, pSetDescriptorBufferOffsetsInfo, VK_PIPELINE_BIND_POINT_COMPUTE); + } - descriptors_state->descriptor_buffers[idx] = cmd_buffer->descriptor_buffers[pBufferIndices[i]] + pOffsets[i]; + if (pSetDescriptorBufferOffsetsInfo->stageFlags & RADV_GRAPHICS_STAGE_BITS) { + radv_set_descriptor_buffer_offsets(cmd_buffer, pSetDescriptorBufferOffsetsInfo, VK_PIPELINE_BIND_POINT_GRAPHICS); + } - radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, NULL, idx); + if (pSetDescriptorBufferOffsetsInfo->stageFlags & RADV_RT_STAGE_BITS) { + radv_set_descriptor_buffer_offsets(cmd_buffer, pSetDescriptorBufferOffsetsInfo, + VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR); } } VKAPI_ATTR void VKAPI_CALL -radv_CmdBindDescriptorBufferEmbeddedSamplersEXT(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, - VkPipelineLayout _layout, uint32_t set) +radv_CmdBindDescriptorBufferEmbeddedSamplers2EXT( + VkCommandBuffer commandBuffer, + const VkBindDescriptorBufferEmbeddedSamplersInfoEXT *pBindDescriptorBufferEmbeddedSamplersInfo) { /* This is a no-op because embedded samplers are inlined at compile time. */ } diff --git a/src/amd/vulkan/radv_device_generated_commands.c b/src/amd/vulkan/radv_device_generated_commands.c index b656ec5018d..486be831fa8 100644 --- a/src/amd/vulkan/radv_device_generated_commands.c +++ b/src/amd/vulkan/radv_device_generated_commands.c @@ -1915,8 +1915,9 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommandsIn radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, cmd_buffer->device->meta_state.dgc_prepare.pipeline); - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), cmd_buffer->device->meta_state.dgc_prepare.p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(params), ¶ms); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), + cmd_buffer->device->meta_state.dgc_prepare.p_layout, VK_SHADER_STAGE_COMPUTE_BIT, 0, + sizeof(params), ¶ms); radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, cmd_buffer->device->meta_state.dgc_prepare.p_layout, 0, ds_cnt, ds_writes); diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index b4ed571d064..fc325a2c43c 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -37,6 +37,7 @@ #include "radv_private.h" #include "sid.h" #include "vk_acceleration_structure.h" +#include "vk_common_entrypoints.h" #define TIMESTAMP_NOT_READY UINT64_MAX @@ -1167,8 +1168,8 @@ radv_query_shader(struct radv_cmd_buffer *cmd_buffer, VkPipeline *pipeline, stru uint32_t uses_gds; } push_constants = {flags, dst_stride, pipeline_stats_mask, avail_offset, uses_gds}; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.query.p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(push_constants), &push_constants); + vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.query.p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(push_constants), &push_constants); cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_INV_VCACHE;
