Module: Mesa Branch: main Commit: 8b7b5be98bc28117e6f4ce144a9d2fa087c18782 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b7b5be98bc28117e6f4ce144a9d2fa087c18782
Author: Samuel Pitoiset <samuel.pitoi...@gmail.com> Date: Tue Jan 2 11:19:34 2024 +0100 radv: disable stencil test without a stencil attachment Implementations are supposed to do that per the Vulkan spec. This fixes the following new VKCTS tests dEQP-VK.pipeline.*.stencil.no_stencil_att.* Cc: mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26847> --- src/amd/vulkan/radv_cmd_buffer.c | 38 +++++++++++++++++++++++--------------- src/amd/vulkan/radv_private.h | 1 + 2 files changed, 24 insertions(+), 15 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 2006eecf27d..df42a603502 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2335,17 +2335,19 @@ radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer) static void radv_emit_depth_control(struct radv_cmd_buffer *cmd_buffer) { + const struct radv_rendering_state *render = &cmd_buffer->state.render; struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; + const bool stencil_test_enable = + d->vk.ds.stencil.test_enable && (render->ds_att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT); - radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, - S_028800_Z_ENABLE(d->vk.ds.depth.test_enable ? 1 : 0) | - S_028800_Z_WRITE_ENABLE(d->vk.ds.depth.write_enable ? 1 : 0) | - S_028800_ZFUNC(d->vk.ds.depth.compare_op) | - S_028800_DEPTH_BOUNDS_ENABLE(d->vk.ds.depth.bounds_test.enable ? 1 : 0) | - S_028800_STENCIL_ENABLE(d->vk.ds.stencil.test_enable ? 1 : 0) | - S_028800_BACKFACE_ENABLE(d->vk.ds.stencil.test_enable ? 1 : 0) | - S_028800_STENCILFUNC(d->vk.ds.stencil.front.op.compare) | - S_028800_STENCILFUNC_BF(d->vk.ds.stencil.back.op.compare)); + radeon_set_context_reg( + cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, + S_028800_Z_ENABLE(d->vk.ds.depth.test_enable ? 1 : 0) | + S_028800_Z_WRITE_ENABLE(d->vk.ds.depth.write_enable ? 1 : 0) | S_028800_ZFUNC(d->vk.ds.depth.compare_op) | + S_028800_DEPTH_BOUNDS_ENABLE(d->vk.ds.depth.bounds_test.enable ? 1 : 0) | + S_028800_STENCIL_ENABLE(stencil_test_enable) | S_028800_BACKFACE_ENABLE(stencil_test_enable) | + S_028800_STENCILFUNC(d->vk.ds.stencil.front.op.compare) | + S_028800_STENCILFUNC_BF(d->vk.ds.stencil.back.op.compare)); } static void @@ -5798,6 +5800,11 @@ radv_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBegi render->ds_att.format = inheritance_info->depthAttachmentFormat; if (inheritance_info->stencilAttachmentFormat != VK_FORMAT_UNDEFINED) render->ds_att.format = inheritance_info->stencilAttachmentFormat; + + if (vk_format_has_depth(render->ds_att.format)) + render->ds_att_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT; + if (vk_format_has_stencil(render->ds_att.format)) + render->ds_att_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT; } cmd_buffer->state.inherited_pipeline_statistics = pBeginInfo->pInheritanceInfo->pipelineStatistics; @@ -7690,6 +7697,7 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe } struct radv_attachment ds_att = {.iview = NULL}; + VkImageAspectFlags ds_att_aspects = 0; const VkRenderingAttachmentInfo *d_att_info = pRenderingInfo->pDepthAttachment; const VkRenderingAttachmentInfo *s_att_info = pRenderingInfo->pStencilAttachment; if ((d_att_info != NULL && d_att_info->imageView != VK_NULL_HANDLE) || @@ -7726,16 +7734,15 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe assert(d_iview == NULL || s_iview == NULL || d_iview == s_iview); ds_att.iview = d_iview ? d_iview : s_iview, ds_att.format = ds_att.iview->vk.format; - VkImageAspectFlags ds_aspects; if (d_iview && s_iview) { - ds_aspects = VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT; + ds_att_aspects = VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT; } else if (d_iview) { - ds_aspects = VK_IMAGE_ASPECT_DEPTH_BIT; + ds_att_aspects = VK_IMAGE_ASPECT_DEPTH_BIT; } else { - ds_aspects = VK_IMAGE_ASPECT_STENCIL_BIT; + ds_att_aspects = VK_IMAGE_ASPECT_STENCIL_BIT; } - radv_initialise_ds_surface(cmd_buffer->device, &ds_att.ds, ds_att.iview, ds_aspects); + radv_initialise_ds_surface(cmd_buffer->device, &ds_att.ds, ds_att.iview, ds_att_aspects); assert(d_res_iview == NULL || s_res_iview == NULL || d_res_iview == s_res_iview); ds_att.resolve_iview = d_res_iview ? d_res_iview : s_res_iview; @@ -7784,6 +7791,7 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe render->color_att_count = pRenderingInfo->colorAttachmentCount; typed_memcpy(render->color_att, color_att, render->color_att_count); render->ds_att = ds_att; + render->ds_att_aspects = ds_att_aspects; render->vrs_att = vrs_att; render->vrs_texel_size = vrs_texel_size; cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER; @@ -7791,7 +7799,7 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe if (cmd_buffer->device->physical_device->rad_info.rbplus_allowed) cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RBPLUS; - cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS; + cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE; if (render->vrs_att.iview && cmd_buffer->device->physical_device->rad_info.gfx_level == GFX10_3) { if (render->ds_att.iview && diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 2af4a0e2cfb..0526d7ecd36 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1390,6 +1390,7 @@ struct radv_rendering_state { uint32_t color_att_count; struct radv_attachment color_att[MAX_RTS]; struct radv_attachment ds_att; + VkImageAspectFlags ds_att_aspects; struct radv_attachment vrs_att; VkExtent2D vrs_texel_size; };
