Module: Mesa Branch: main Commit: b5c0b9040218569ce13efcd0d87664e93b48f8b7 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5c0b9040218569ce13efcd0d87664e93b48f8b7
Author: Sviatoslav Peleshko <sviatoslav.peles...@globallogic.com> Date: Wed Oct 11 11:04:12 2023 +0300 intel/compiler: Set flag reg to 0 when disabling predication Having the reg set with predication disabled shouldn't cause any problems during the execution. But when decompiling such instruction the flag won't be shown in the output, so the recompiling will cause functionally-identical but binary-different code. Fixing this makes disasm/asm testing easier. Signed-off-by: Sviatoslav Peleshko <sviatoslav.peles...@globallogic.com> Reviewed-by: Sagar Ghuge <sagar.gh...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657> --- src/intel/compiler/brw_eu_emit.c | 6 ++++++ src/intel/compiler/brw_fs_generator.cpp | 3 +++ src/intel/compiler/brw_vec4_generator.cpp | 5 +++++ 3 files changed, 14 insertions(+) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 0dd7b3ac266..9d312a6400f 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -2457,6 +2457,7 @@ void brw_oword_block_read(struct brw_codegen *p, brw_push_insn_state(p); brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + brw_set_default_flag_reg(p, 0, 0); brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); brw_set_default_mask_control(p, BRW_MASK_DISABLE); @@ -2766,6 +2767,7 @@ brw_send_indirect_message(struct brw_codegen *p, brw_set_default_mask_control(p, BRW_MASK_DISABLE); brw_set_default_exec_size(p, BRW_EXECUTE_1); brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + brw_set_default_flag_reg(p, 0, 0); brw_set_default_swsb(p, tgl_swsb_src_dep(swsb)); /* Load the indirect descriptor to an address register using OR so the @@ -2823,6 +2825,7 @@ brw_send_indirect_split_message(struct brw_codegen *p, brw_set_default_mask_control(p, BRW_MASK_DISABLE); brw_set_default_exec_size(p, BRW_EXECUTE_1); brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + brw_set_default_flag_reg(p, 0, 0); brw_set_default_swsb(p, tgl_swsb_src_dep(swsb)); /* Load the indirect descriptor to an address register using OR so the @@ -2857,6 +2860,7 @@ brw_send_indirect_split_message(struct brw_codegen *p, brw_set_default_mask_control(p, BRW_MASK_DISABLE); brw_set_default_exec_size(p, BRW_EXECUTE_1); brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + brw_set_default_flag_reg(p, 0, 0); brw_set_default_swsb(p, tgl_swsb_src_dep(swsb)); /* Load the indirect extended descriptor to an address register using OR @@ -2953,6 +2957,7 @@ brw_send_indirect_surface_message(struct brw_codegen *p, brw_set_default_mask_control(p, BRW_MASK_DISABLE); brw_set_default_exec_size(p, BRW_EXECUTE_1); brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + brw_set_default_flag_reg(p, 0, 0); brw_set_default_swsb(p, tgl_swsb_src_dep(swsb)); /* Mask out invalid bits from the surface index to avoid hangs e.g. when @@ -3570,6 +3575,7 @@ brw_broadcast(struct brw_codegen *p, brw_push_insn_state(p); brw_set_default_mask_control(p, BRW_MASK_DISABLE); brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + brw_set_default_flag_reg(p, 0, 0); /* Take into account the component size and horizontal stride. */ assert(src.vstride == src.hstride + src.width); diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index a3481d159c3..3331676939f 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -369,6 +369,7 @@ fs_generator::fire_fb_write(fs_inst *inst, brw_set_default_exec_size(p, BRW_EXECUTE_8); brw_set_default_mask_control(p, BRW_MASK_DISABLE); brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + brw_set_default_flag_reg(p, 0, 0); brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); brw_MOV(p, offset(retype(payload, BRW_REGISTER_TYPE_UD), 1), offset(retype(implied_header, BRW_REGISTER_TYPE_UD), 1)); @@ -1681,6 +1682,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, brw_set_default_exec_size(p, BRW_EXECUTE_16); brw_set_default_mask_control(p, BRW_MASK_DISABLE); brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + brw_set_default_flag_reg(p, 0, 0); brw_set_default_swsb(p, tgl_swsb_src_dep(swsb)); brw_MOV(p, brw_acc_reg(8), brw_imm_f(0.0f)); last_insn_offset = p->next_insn_offset; @@ -1701,6 +1703,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, brw_set_default_exec_size(p, BRW_EXECUTE_1); brw_set_default_mask_control(p, BRW_MASK_DISABLE); brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + brw_set_default_flag_reg(p, 0, 0); brw_set_default_swsb(p, tgl_swsb_src_dep(swsb)); brw_SYNC(p, TGL_SYNC_NOP); last_insn_offset = p->next_insn_offset; diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp index a62ca3df242..fbd58f5c66a 100644 --- a/src/intel/compiler/brw_vec4_generator.cpp +++ b/src/intel/compiler/brw_vec4_generator.cpp @@ -93,6 +93,7 @@ generate_math2_gfx4(struct brw_codegen *p, brw_push_insn_state(p); brw_set_default_saturate(p, false); brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + brw_set_default_flag_reg(p, 0, 0); brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1); brw_pop_insn_state(p); @@ -1198,7 +1199,9 @@ generate_scratch_write(struct brw_codegen *p, /* If the instruction is predicated, we'll predicate the send, not * the header setup. */ + brw_push_insn_state(p); brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); + brw_set_default_flag_reg(p, 0, 0); gfx6_resolve_implied_move(p, &header, inst->base_mrf); @@ -1209,6 +1212,8 @@ generate_scratch_write(struct brw_codegen *p, retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D), retype(src, BRW_REGISTER_TYPE_D)); + brw_pop_insn_state(p); + uint32_t msg_type; if (devinfo->ver >= 7)
