Module: Mesa
Branch: main
Commit: 98d2461424960e492c923a604308b7b3e5967296
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=98d2461424960e492c923a604308b7b3e5967296
Author: Sviatoslav Peleshko <sviatoslav.peles...@globallogic.com>
Date: Wed Oct 11 13:32:53 2023 +0300
intel/tools/i965_asm: Don't set src0 for break and while on gfx12
This effectively implements same changes as were done to codegen in
bafc9515 ("intel/eu/gen12: Codegen control flow instructions correctly.")
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peles...@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.gh...@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
---
src/intel/tools/i965_gram.y | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/intel/tools/i965_gram.y b/src/intel/tools/i965_gram.y
index c9f0c6cec6c..06e0cb8c228 100644
--- a/src/intel/tools/i965_gram.y
+++ b/src/intel/tools/i965_gram.y
@@ -1432,12 +1432,12 @@ breakinstruction:
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
- if (p->devinfo->ver >= 8) {
- brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
- } else {
+ if (p->devinfo->ver < 8) {
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
+ } else if (p->devinfo->ver < 12) {
+ brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
}
brw_pop_insn_state(p);
@@ -1492,7 +1492,8 @@ loopinstruction:
brw_set_dest(p, brw_last_inst,
retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
- brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
+ if (p->devinfo->ver < 12)
+ brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
} else if (p->devinfo->ver == 7) {
brw_set_dest(p, brw_last_inst,
retype(brw_null_reg(),
