Module: Mesa Branch: main Commit: 8e6d28f4734158182c722898e4469b121a5f4b12 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e6d28f4734158182c722898e4469b121a5f4b12
Author: Sviatoslav Peleshko <sviatoslav.peles...@globallogic.com> Date: Wed Oct 11 13:45:05 2023 +0300 intel/tools/tests: Add i965_asm tests for gfx12 and gfx12.5 Signed-off-by: Sviatoslav Peleshko <sviatoslav.peles...@globallogic.com> Reviewed-by: Sagar Ghuge <sagar.gh...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657> --- src/intel/tools/meson.build | 2 ++ src/intel/tools/tests/gen12.5/add3.asm | 7 +++++ src/intel/tools/tests/gen12.5/add3.expected | 7 +++++ src/intel/tools/tests/gen12.5/send.asm | 30 ++++++++++++++++++++ src/intel/tools/tests/gen12.5/send.expected | 15 ++++++++++ src/intel/tools/tests/gen12.5/swsb.asm | 23 +++++++++++++++ src/intel/tools/tests/gen12.5/swsb.expected | 21 ++++++++++++++ src/intel/tools/tests/gen12/dp4a.asm | 33 ++++++++++++++++++++++ src/intel/tools/tests/gen12/dp4a.expected | 33 ++++++++++++++++++++++ src/intel/tools/tests/gen12/send.asm | 43 +++++++++++++++++++++++++++++ src/intel/tools/tests/gen12/send.expected | 21 ++++++++++++++ src/intel/tools/tests/gen12/swsb.asm | 40 +++++++++++++++++++++++++++ src/intel/tools/tests/gen12/swsb.expected | 38 +++++++++++++++++++++++++ src/intel/tools/tests/gen12/sync.asm | 33 ++++++++++++++++++++++ src/intel/tools/tests/gen12/sync.expected | 33 ++++++++++++++++++++++ 15 files changed, 379 insertions(+) diff --git a/src/intel/tools/meson.build b/src/intel/tools/meson.build index 98c4d995bfb..8c6009d64d6 100644 --- a/src/intel/tools/meson.build +++ b/src/intel/tools/meson.build @@ -241,6 +241,8 @@ asm_testcases = [ ['bdw', 'gfx8'], ['skl', 'gfx9'], ['icl', 'gfx11'], + ['tgl', 'gfx12'], + ['dg2', 'gfx12.5'], ] test_runner = find_program('tests/run-test.py') diff --git a/src/intel/tools/tests/gen12.5/add3.asm b/src/intel/tools/tests/gen12.5/add3.asm new file mode 100644 index 00000000000..1e81dd0031f --- /dev/null +++ b/src/intel/tools/tests/gen12.5/add3.asm @@ -0,0 +1,7 @@ +add3(8) g118<1>D -g117<8,8,1>D g114<8,8,1>D g115<1,1,1>D { align1 1Q I@2 }; +add3(16) g55<1>D g50<8,8,1>D g46<8,8,1>D -g53<1,1,1>D { align1 1H @2 $5.dst }; +add3(16) g111<1>D -g40<8,8,1>D -g88<8,8,1>D g111<1,1,1>D { align1 1H I@1 }; +add3(16) g49<1>D 0x0008UW g47<8,8,1>D g26<1,1,1>D { align1 1H I@4 }; +add3(16) g55<1>D 0x0008UW g53<8,8,1>D g65<1,1,1>D { align1 2H I@3 }; +add3(8) g57<1>D g52<8,8,1>D (abs)g48<8,8,1>D (abs)g59<1,1,1>D { align1 1Q I@4 }; +add3(16) g51<1>D g63<8,8,1>D -g122<8,8,1>D (abs)g27<1,1,1>D { align1 1H I@7 }; diff --git a/src/intel/tools/tests/gen12.5/add3.expected b/src/intel/tools/tests/gen12.5/add3.expected new file mode 100644 index 00000000000..e6146920beb --- /dev/null +++ b/src/intel/tools/tests/gen12.5/add3.expected @@ -0,0 +1,7 @@ +52 1a 03 00 68 2e 04 76 05 75 0e 0e 05 72 05 73 +52 a5 04 00 68 0e 04 37 05 32 2e 0e 05 2e 05 35 +52 19 04 00 68 2e 04 6f 05 28 8e 0e 05 58 05 6f +52 1c 04 00 60 41 04 31 08 00 0e 0e 05 2f 05 1a +52 1b 24 00 60 41 04 37 08 00 0e 0e 05 35 05 41 +52 1c 03 00 68 0e 04 39 05 34 5e 0e 05 30 05 3b +52 1f 04 00 68 0e 04 33 05 3f 9e 0e 05 7a 05 1b diff --git a/src/intel/tools/tests/gen12.5/send.asm b/src/intel/tools/tests/gen12.5/send.asm new file mode 100644 index 00000000000..6321737809f --- /dev/null +++ b/src/intel/tools/tests/gen12.5/send.asm @@ -0,0 +1,30 @@ +(+f0.0.any8h) send(1) g57UD g58UD nullUD 0x6210c500 0x02000000 + ugm MsgDesc: ( load, a32, d32, V8, transpose, L1STATE_L3MOCS dst_len = 1, src0_len = 1, src1_len = 0 bti ) BTI 2 base_offset 0 { align1 WE_all 1N $5 }; +(+f0.0.any8h) send(1) g28UD g29UD nullUD 0x6210c500 0x02000000 + ugm MsgDesc: ( load, a32, d32, V8, transpose, L1STATE_L3MOCS dst_len = 1, src0_len = 1, src1_len = 0 bti ) BTI 2 base_offset 0 { align1 WE_all 1N $2 }; +(+f0.0.any32h) send(1) g57UD g58UD nullUD 0x6210c500 0x02000000 + ugm MsgDesc: ( load, a32, d32, V8, transpose, L1STATE_L3MOCS dst_len = 1, src0_len = 1, src1_len = 0 bti ) BTI 2 base_offset 0 { align1 WE_all 1N $0 }; +send(8) nullUD g79UD g10UD 0x6200f506 0x04000100 + ugm MsgDesc: ( store_cmask, a32, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 1, src1_len = 4 bti ) BTI 4 base_offset 0 { align1 1Q $0 }; +send(16) nullUD g9UD g7UD 0x44000504 a0.1<0>UD + ugm MsgDesc: ( store, a32, d32, V1, L1STATE_L3MOCS dst_len = 0, src0_len = 2, src1_len = 0 ss ) surface_state_index 0 { align1 1H @1 $0 }; +send(1) g4UD g0UD nullUD 0x0210151f 0x00000000 + tgm MsgDesc: ( fence, a32, tile, evict, normal_routing dst_len = 1, src0_len = 1, src1_len = 0 flat ) base_offset 0 { align1 WE_all 1N $3 }; +send(8) nullUD g36UD g37UD 0x02000b04 0x00000040 + slm MsgDesc: ( store, a32, d16u32, V1, L1STATE_L3MOCS dst_len = 0, src0_len = 1, src1_len = 1 flat ) base_offset 0 { align1 1Q $1 }; +send(8) nullUD g34UD g35UD 0x02000b04 0x00000040 + slm MsgDesc: ( store, a32, d16u32, V1, L1STATE_L3MOCS dst_len = 0, src0_len = 1, src1_len = 1 flat ) base_offset 0 { align1 1Q $0 }; +send(8) nullUD g6UD g7UD 0x0200f506 0x00000100 + slm MsgDesc: ( store_cmask, a32, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 1, src1_len = 4 flat ) base_offset 0 { align1 1Q $6 }; +send(16) nullUD g82UD g91UD 0x04040519 0x00000080 + slm MsgDesc: ( atomic_or, a32, d32, V1, L1UC_L3WB dst_len = 0, src0_len = 2, src1_len = 2 flat ) base_offset 0 { align1 2H $0 }; +send(1) g10UD g0UD nullUD 0x0210011f 0x00000000 + slm MsgDesc: ( fence, a32, threadgroup, none, normal_routing dst_len = 1, src0_len = 1, src1_len = 0 flat ) base_offset 0 { align1 WE_all 1N $1 }; +send(1) g23UD g117UD nullUD 0x2210c500 a0.1<0>UD + ugm MsgDesc: ( load, a32, d32, V8, transpose, L1STATE_L3MOCS dst_len = 1, src0_len = 1, bss ) src1_len = 0 ex_bso surface_state_index 0 { align1 WE_all 1N @1 $10 }; +send(8) nullUD g14UD g24UD 0x040350fc a0.1<0>UD + dp data 1 MsgDesc: (DC typed surface write, Surface = 252, SIMD16, Mask = 0x0) src1_len = 4 ex_bso mlen 2 rlen 0 { align1 1Q @1 $5 }; +send(8) nullUD g51UD g52UD 0x02000000 0x00000040 + rt accel MsgDesc: SIMD8, mlen 1 ex_mlen 1 rlen 0 { align1 1Q $2 }; +send(16) nullUD g88UD g98UD 0x02000100 0x00000080 + rt accel MsgDesc: SIMD16, mlen 1 ex_mlen 2 rlen 0 { align1 1H $6 }; diff --git a/src/intel/tools/tests/gen12.5/send.expected b/src/intel/tools/tests/gen12.5/send.expected new file mode 100644 index 00000000000..51616dd2b3d --- /dev/null +++ b/src/intel/tools/tests/gen12.5/send.expected @@ -0,0 +1,15 @@ +31 45 00 88 00 00 0c 39 8e 3a 00 fa 00 00 30 04 +31 42 00 88 00 00 0c 1c 8e 1d 00 fa 00 00 30 04 +31 40 00 8c 00 00 0c 39 8e 3a 00 fa 00 00 30 04 +31 40 03 00 00 00 00 00 8c 4f 0c fa 25 0a 3c 04 +31 90 04 00 00 01 02 00 14 09 08 fa 04 07 00 04 +31 43 00 80 00 00 0c 04 0c 00 3e da 00 00 04 00 +31 41 03 00 00 00 00 00 0c 24 08 e6 0c 25 02 00 +31 40 03 00 00 00 00 00 0c 22 08 e6 0c 23 02 00 +31 46 03 00 00 00 00 00 0c 06 0c ea 24 07 3c 00 +31 40 24 00 00 00 00 00 14 52 32 ea 14 5b 00 01 +31 41 00 80 00 00 0c 0a 0c 00 3e e2 00 00 00 00 +31 9a 00 80 80 01 0e 17 8c 75 00 fa 00 00 30 00 +31 95 03 00 80 01 02 00 14 0e f8 c1 24 18 d4 00 +31 42 03 00 00 00 00 00 0c 33 00 80 0c 34 00 00 +31 46 04 00 00 00 00 00 0c 58 00 82 14 62 00 00 diff --git a/src/intel/tools/tests/gen12.5/swsb.asm b/src/intel/tools/tests/gen12.5/swsb.asm new file mode 100644 index 00000000000..4a7b9af8daf --- /dev/null +++ b/src/intel/tools/tests/gen12.5/swsb.asm @@ -0,0 +1,23 @@ +mul(8) g37<1>D g99<8,8,1>D g36<16,8,2>UW { align1 1Q I@1 }; +mul(8) g37<1>D g99<8,8,1>D g36<16,8,2>UW { align1 1Q I@2 }; +mul(8) g37<1>D g99<8,8,1>D g36<16,8,2>UW { align1 1Q I@3 }; +mul(8) g37<1>D g99<8,8,1>D g36<16,8,2>UW { align1 1Q I@4 }; +mul(8) g37<1>D g99<8,8,1>D g36<16,8,2>UW { align1 1Q I@5 }; +mul(8) g37<1>D g99<8,8,1>D g36<16,8,2>UW { align1 1Q I@6 }; +mul(8) g37<1>D g99<8,8,1>D g36<16,8,2>UW { align1 1Q I@7 }; + +mov(8) g36<1>UD g35<8,8,1>F { align1 1Q F@1 }; +mov(8) g36<1>UD g35<8,8,1>F { align1 1Q F@2 }; +mov(8) g36<1>UD g35<8,8,1>F { align1 1Q F@3 }; +mov(8) g36<1>UD g35<8,8,1>F { align1 1Q F@4 }; +mov(8) g36<1>UD g35<8,8,1>F { align1 1Q F@5 }; +mov(8) g36<1>UD g35<8,8,1>F { align1 1Q F@6 }; +mov(8) g36<1>UD g35<8,8,1>F { align1 1Q F@7 }; + +add(1) a0<1>UD a0<0,1,0>UD 0x00000800UD { align1 WE_all 1N A@1 }; +add(1) a0<1>UD a0<0,1,0>UD 0x00000800UD { align1 WE_all 1N A@2 }; +add(1) a0<1>UD a0<0,1,0>UD 0x00000800UD { align1 WE_all 1N A@3 }; +add(1) a0<1>UD a0<0,1,0>UD 0x00000800UD { align1 WE_all 1N A@4 }; +add(1) a0<1>UD a0<0,1,0>UD 0x00000800UD { align1 WE_all 1N A@5 }; +add(1) a0<1>UD a0<0,1,0>UD 0x00000800UD { align1 WE_all 1N A@6 }; +add(1) a0<1>UD a0<0,1,0>UD 0x00000800UD { align1 WE_all 1N A@7 }; \ No newline at end of file diff --git a/src/intel/tools/tests/gen12.5/swsb.expected b/src/intel/tools/tests/gen12.5/swsb.expected new file mode 100644 index 00000000000..fef186c7079 --- /dev/null +++ b/src/intel/tools/tests/gen12.5/swsb.expected @@ -0,0 +1,21 @@ +41 19 03 00 60 06 05 25 05 63 46 01 06 24 56 00 +41 1a 03 00 60 06 05 25 05 63 46 01 06 24 56 00 +41 1b 03 00 60 06 05 25 05 63 46 01 06 24 56 00 +41 1c 03 00 60 06 05 25 05 63 46 01 06 24 56 00 +41 1d 03 00 60 06 05 25 05 63 46 01 06 24 56 00 +41 1e 03 00 60 06 05 25 05 63 46 01 06 24 56 00 +41 1f 03 00 60 06 05 25 05 63 46 01 06 24 56 00 +61 11 03 00 20 0a 05 24 05 23 46 00 00 00 00 00 +61 12 03 00 20 0a 05 24 05 23 46 00 00 00 00 00 +61 13 03 00 20 0a 05 24 05 23 46 00 00 00 00 00 +61 14 03 00 20 0a 05 24 05 23 46 00 00 00 00 00 +61 15 03 00 20 0a 05 24 05 23 46 00 00 00 00 00 +61 16 03 00 20 0a 05 24 05 23 46 00 00 00 00 00 +61 17 03 00 20 0a 05 24 05 23 46 00 00 00 00 00 +40 09 00 80 20 82 01 10 00 10 00 02 00 08 00 00 +40 0a 00 80 20 82 01 10 00 10 00 02 00 08 00 00 +40 0b 00 80 20 82 01 10 00 10 00 02 00 08 00 00 +40 0c 00 80 20 82 01 10 00 10 00 02 00 08 00 00 +40 0d 00 80 20 82 01 10 00 10 00 02 00 08 00 00 +40 0e 00 80 20 82 01 10 00 10 00 02 00 08 00 00 +40 0f 00 80 20 82 01 10 00 10 00 02 00 08 00 00 diff --git a/src/intel/tools/tests/gen12/dp4a.asm b/src/intel/tools/tests/gen12/dp4a.asm new file mode 100644 index 00000000000..5ae00c8aae3 --- /dev/null +++ b/src/intel/tools/tests/gen12/dp4a.asm @@ -0,0 +1,33 @@ +dp4a(8) g10<1>D g2<8,8,1>D g6<8,8,1>D g7<1,1,1>D { align1 1Q @1 }; +dp4a(8) g10<1>D g2<8,8,1>D g6<8,8,1>D g7<1,1,1>UD { align1 1Q @1 }; +dp4a(8) g10<1>D g2<8,8,1>D g8<8,8,1>D g9<1,1,1>D { align1 1Q @1 }; +dp4a(8) g10<1>D g2<8,8,1>D g8<8,8,1>D g9<1,1,1>UD { align1 1Q @1 }; +dp4a(8) g10<1>UD g2<8,8,1>UD g6<8,8,1>UD g7<1,1,1>UD { align1 1Q @1 }; +dp4a(8) g10<1>UD g2<8,8,1>UD g8<8,8,1>UD g9<1,1,1>UD { align1 1Q @1 }; +dp4a(8) g5<1>D g2<8,8,1>D g3<8,8,1>D g4<1,1,1>D { align1 1Q @3 $0.dst }; +dp4a(8) g5<1>D g2<8,8,1>D g3<8,8,1>D g4<1,1,1>UD { align1 1Q @3 $0.dst }; +dp4a(8) g5<1>UD g2<8,8,1>UD g3<8,8,1>UD g4<1,1,1>UD { align1 1Q @3 $0.dst }; +dp4a(8) g6<1>D g2<8,8,1>D g3<8,8,1>D g4<1,1,1>D { align1 1Q @4 $1.dst }; +dp4a(8) g6<1>D g2<8,8,1>D g3<8,8,1>D g4<1,1,1>UD { align1 1Q @4 $1.dst }; +dp4a(8) g6<1>D g2<8,8,1>D g4<8,8,1>D g5<1,1,1>D { align1 1Q @4 $0.dst }; +dp4a(8) g6<1>D g2<8,8,1>D g4<8,8,1>D g5<1,1,1>UD { align1 1Q @4 $0.dst }; +dp4a(8) g6<1>UD g2<8,8,1>UD g3<8,8,1>UD g4<1,1,1>UD { align1 1Q @4 $1.dst }; +dp4a(8) g6<1>UD g2<8,8,1>UD g4<8,8,1>UD g5<1,1,1>UD { align1 1Q @4 $0.dst }; +dp4a(8) g7<1>D g2<8,8,1>D g5<8,8,1>D g6<1,1,1>D { align1 1Q @1 }; +dp4a(8) g7<1>D g2<8,8,1>D g5<8,8,1>D g6<1,1,1>UD { align1 1Q @1 }; +dp4a(8) g7<1>UD g2<8,8,1>UD g5<8,8,1>UD g6<1,1,1>UD { align1 1Q @1 }; +dp4a(8) g8<1>D g2<8,8,1>D g4<8,8,1>D g5<1,1,1>D { align1 1Q @3 $0.dst }; +dp4a(8) g8<1>D g2<8,8,1>D g4<8,8,1>D g5<1,1,1>D { align1 1Q @4 $0.dst }; +dp4a(8) g8<1>D g2<8,8,1>D g4<8,8,1>D g5<1,1,1>UD { align1 1Q @3 $0.dst }; +dp4a(8) g8<1>D g2<8,8,1>D g4<8,8,1>D g5<1,1,1>UD { align1 1Q @4 $0.dst }; +dp4a(8) g8<1>D g2<8,8,1>D g6<8,8,1>D g7<1,1,1>D { align1 1Q @1 }; +dp4a(8) g8<1>D g2<8,8,1>D g6<8,8,1>D g7<1,1,1>UD { align1 1Q @1 }; +dp4a(8) g8<1>UD g2<8,8,1>UD g4<8,8,1>UD g5<1,1,1>UD { align1 1Q @3 $0.dst }; +dp4a(8) g8<1>UD g2<8,8,1>UD g4<8,8,1>UD g5<1,1,1>UD { align1 1Q @4 $0.dst }; +dp4a(8) g8<1>UD g2<8,8,1>UD g6<8,8,1>UD g7<1,1,1>UD { align1 1Q @1 }; +dp4a.sat(8) g10<1>D g5<8,8,1>D g6<8,8,1>D g7<1,1,1>D { align1 1Q @1 $2.dst }; +dp4a.sat(8) g10<1>D g5<8,8,1>D g6<8,8,1>D g7<1,1,1>UD { align1 1Q @1 $2.dst }; +dp4a.sat(8) g10<1>UD g5<8,8,1>UD g6<8,8,1>UD g7<1,1,1>UD { align1 1Q @1 $2.dst }; +dp4a.sat(8) g8<1>D g5<8,8,1>D g3<8,8,1>D g4<1,1,1>D { align1 1Q $2.dst }; +dp4a.sat(8) g8<1>D g5<8,8,1>D g3<8,8,1>D g4<1,1,1>UD { align1 1Q $2.dst }; +dp4a.sat(8) g8<1>UD g5<8,8,1>UD g3<8,8,1>UD g4<1,1,1>UD { align1 1Q $2.dst }; diff --git a/src/intel/tools/tests/gen12/dp4a.expected b/src/intel/tools/tests/gen12/dp4a.expected new file mode 100644 index 00000000000..44904c296ff --- /dev/null +++ b/src/intel/tools/tests/gen12/dp4a.expected @@ -0,0 +1,33 @@ +58 01 03 00 68 0e 04 0a 05 02 0e 0e 05 06 05 07 +58 01 03 00 68 0e 04 0a 05 02 0a 0e 05 06 05 07 +58 01 03 00 68 0e 04 0a 05 02 0e 0e 05 08 05 09 +58 01 03 00 68 0e 04 0a 05 02 0a 0e 05 08 05 09 +58 01 03 00 28 0a 04 0a 05 02 0a 0a 05 06 05 07 +58 01 03 00 28 0a 04 0a 05 02 0a 0a 05 08 05 09 +58 b0 03 00 68 0e 04 05 05 02 0e 0e 05 03 05 04 +58 b0 03 00 68 0e 04 05 05 02 0a 0e 05 03 05 04 +58 b0 03 00 28 0a 04 05 05 02 0a 0a 05 03 05 04 +58 c1 03 00 68 0e 04 06 05 02 0e 0e 05 03 05 04 +58 c1 03 00 68 0e 04 06 05 02 0a 0e 05 03 05 04 +58 c0 03 00 68 0e 04 06 05 02 0e 0e 05 04 05 05 +58 c0 03 00 68 0e 04 06 05 02 0a 0e 05 04 05 05 +58 c1 03 00 28 0a 04 06 05 02 0a 0a 05 03 05 04 +58 c0 03 00 28 0a 04 06 05 02 0a 0a 05 04 05 05 +58 01 03 00 68 0e 04 07 05 02 0e 0e 05 05 05 06 +58 01 03 00 68 0e 04 07 05 02 0a 0e 05 05 05 06 +58 01 03 00 28 0a 04 07 05 02 0a 0a 05 05 05 06 +58 b0 03 00 68 0e 04 08 05 02 0e 0e 05 04 05 05 +58 c0 03 00 68 0e 04 08 05 02 0e 0e 05 04 05 05 +58 b0 03 00 68 0e 04 08 05 02 0a 0e 05 04 05 05 +58 c0 03 00 68 0e 04 08 05 02 0a 0e 05 04 05 05 +58 01 03 00 68 0e 04 08 05 02 0e 0e 05 06 05 07 +58 01 03 00 68 0e 04 08 05 02 0a 0e 05 06 05 07 +58 b0 03 00 28 0a 04 08 05 02 0a 0a 05 04 05 05 +58 c0 03 00 28 0a 04 08 05 02 0a 0a 05 04 05 05 +58 01 03 00 28 0a 04 08 05 02 0a 0a 05 06 05 07 +58 92 03 00 6c 0e 04 0a 05 05 0e 0e 05 06 05 07 +58 92 03 00 6c 0e 04 0a 05 05 0a 0e 05 06 05 07 +58 92 03 00 2c 0a 04 0a 05 05 0a 0a 05 06 05 07 +58 22 03 00 6c 0e 04 08 05 05 0e 0e 05 03 05 04 +58 22 03 00 6c 0e 04 08 05 05 0a 0e 05 03 05 04 +58 22 03 00 2c 0a 04 08 05 05 0a 0a 05 03 05 04 diff --git a/src/intel/tools/tests/gen12/send.asm b/src/intel/tools/tests/gen12/send.asm new file mode 100644 index 00000000000..81119aa8ccf --- /dev/null +++ b/src/intel/tools/tests/gen12/send.asm @@ -0,0 +1,43 @@ +send(16) g113UD g12UD nullUD a0<0>UD 0x00000000 + dp data 1 MsgDesc: indirect ex_mlen 0 { align1 1H @1 $6 }; +(+f1.0) send(16) nullUD g15UD g17UD a0<0>UD 0x00000080 + dp data 1 MsgDesc: indirect ex_mlen 2 { align1 1H @1 $4 }; +send(8) g104UD g119UD nullUD 0x04116e13 0x00000000 + dp data 1 MsgDesc: (DC typed surface read, Surface = 19, SIMD8, Mask = 0xe) mlen 2 ex_mlen 0 rlen 1 { align1 2Q $8 }; +send(8) nullUD g92UD g117UD 0x020350fc a0.1<0>UD + dp data 1 MsgDesc: (DC typed surface write, Surface = 252, SIMD16, Mask = 0x0) mlen 1 rlen 0 { align1 1Q @1 $8 }; +(+f0.0.any8h) send(8) g55UD g118UD nullUD 0x02184201 0x00000000 + data MsgDesc: (DC unaligned OWORD block read, bti 1, 2) mlen 1 ex_mlen 0 rlen 1 { align1 WE_all 1Q @3 $9 }; +send(8) nullUD g126UD nullUD 0x02000000 0x00000000 + thread_spawner MsgDesc: mlen 1 ex_mlen 0 rlen 0 { align1 WE_all 1Q @1 EOT }; +send(8) g18UD g24UD nullUD 0x04115e10 0x00000000 + dp data 1 MsgDesc: (DC typed surface read, Surface = 16, SIMD16, Mask = 0xe) mlen 2 ex_mlen 0 rlen 1 { align1 1Q $1 }; +send(8) g19UD g28UD nullUD 0x04116e10 0x00000000 + dp data 1 MsgDesc: (DC typed surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 2 ex_mlen 0 rlen 1 { align1 2Q @7 $2 }; +send(16) g50UD g36UD nullUD a0<0>UD 0x00000000 + sampler MsgDesc: indirect ex_mlen 0 { align1 1H @1 $3 }; +send(8) nullUD g25UD g21UD 0x02035001 0x00000100 + dp data 1 MsgDesc: (DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q $9 }; +send(8) g5UD g25UD nullUD 0x02415001 0x00000000 + dp data 1 MsgDesc: (DC typed surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 1 ex_mlen 0 rlen 4 { align1 1Q $10 }; +send(8) g27UD g35UD nullUD 0x04146efd 0x00000000 + dp data 1 MsgDesc: (DC A64 untyped surface read, Surface = 253, SIMD8, Mask = 0xe) mlen 2 ex_mlen 0 rlen 1 { align1 1Q @1 $0 }; +send(8) nullUD g36UD g38UD 0x04035001 0x00000100 + dp data 1 MsgDesc: (DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q @1 $1 }; +send(8) nullUD g126UD g118UD 0x02080007 0x00000200 + urb MsgDesc: offset 0 SIMD8 write mlen 1 ex_mlen 8 rlen 0 { align1 1Q @1 EOT }; +send(8) g14UD g37UD nullUD 0x02110401 0x00000000 + data MsgDesc: (DC byte scattered read, bti 1, 4) mlen 1 ex_mlen 0 rlen 1 { align1 1Q @1 $0 }; +send(1) g100UD g0UD nullUD 0x0219e000 0x00000000 + data MsgDesc: (DC mfence, bti 0, 32) mlen 1 ex_mlen 0 rlen 1 { align1 WE_all 1N $1 }; +send(1) g15UD g0UD nullUD 0x0219e000 0x00000000 + data MsgDesc: (DC mfence, bti 0, 32) mlen 1 ex_mlen 0 rlen 1 { align1 WE_all 1N $5 }; + +sendc(16) nullUD g119UD nullUD 0x10031000 0x00000000 + render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 ex_mlen 0 rlen 0 { align1 1H @1 EOT }; +sendc(8) nullUD g125UD g123UD 0x04031400 0x00000080 + render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 2 ex_mlen 2 rlen 0 { align1 1Q @1 EOT }; +sendc(16) nullUD g119UD nullUD 0x10031000 0x00000000 + render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 ex_mlen 0 rlen 0 { align1 1H @1 EOT }; +sendc(16) nullUD g123UD g119UD 0x08031000 0x00000100 + render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 4 ex_mlen 4 rlen 0 { align1 1H @1 EOT }; diff --git a/src/intel/tools/tests/gen12/send.expected b/src/intel/tools/tests/gen12/send.expected new file mode 100644 index 00000000000..3ba1ebb53c2 --- /dev/null +++ b/src/intel/tools/tests/gen12/send.expected @@ -0,0 +1,21 @@ +31 96 04 00 00 00 05 71 04 0c 00 c0 00 00 00 00 +31 94 84 01 00 00 01 00 04 0f 00 c0 14 11 00 00 +31 48 13 00 00 00 0c 68 14 77 26 cc 00 00 5a 00 +31 98 03 00 00 01 02 00 0c 5c f8 c1 04 75 d4 00 +31 b9 03 88 00 00 0c 37 0c 76 02 a4 00 00 10 02 +31 01 03 80 04 00 00 00 0c 7e 00 70 00 00 00 00 +31 41 03 00 00 00 0c 12 14 18 20 cc 00 00 56 00 +31 f2 13 00 00 00 0c 13 14 1c 20 cc 00 00 5a 00 +31 93 04 00 00 00 05 32 04 24 00 20 00 00 00 00 +31 49 03 00 00 00 00 00 0c 19 02 c0 24 15 d4 00 +31 4a 03 00 00 00 24 05 0c 19 02 c0 00 00 54 00 +31 90 03 00 00 00 0c 1b 14 23 fa cd 00 00 1a 01 +31 91 03 00 00 00 00 00 14 24 02 c0 24 26 d4 00 +31 01 03 00 04 00 00 00 0c 7e 0e 60 44 76 00 02 +31 90 03 00 00 00 0c 0e 0c 25 02 a8 00 00 40 00 +31 41 00 80 00 00 0c 64 0c 00 00 a0 00 00 78 02 +31 45 00 80 00 00 0c 0f 0c 00 00 a0 00 00 78 02 +32 01 04 00 04 00 00 00 44 77 00 50 00 00 c4 00 +32 01 03 00 04 00 00 00 14 7d 00 58 14 7b c4 00 +32 01 04 00 04 00 00 00 44 77 00 50 00 00 c4 00 +32 01 04 00 04 00 00 00 24 7b 00 50 24 77 c4 00 diff --git a/src/intel/tools/tests/gen12/swsb.asm b/src/intel/tools/tests/gen12/swsb.asm new file mode 100644 index 00000000000..7c813356cf3 --- /dev/null +++ b/src/intel/tools/tests/gen12/swsb.asm @@ -0,0 +1,40 @@ +cmp.l.f0.0(8) g55<1>UD g54<8,8,1>UD 0x00000290UD { align1 1Q @1 }; +mov(16) g6<1>D g20<8,8,1>W { align1 2H @2 }; +add(16) g122<1>F g98<8,8,1>F (abs)g102<8,8,1>F { align1 1H @3 }; +shl(8) g75<1>D g122<8,8,1>D 0x00000002UD { align1 1Q @4 }; +sel.l(4) g90.4<1>D g90.3<0,1,0>D g90.4<4,4,1>D { align1 WE_all 1N @5 }; +and(16) g58<1>UD g16<8,8,1>UD g56<8,8,1>UD { align1 1H @6 }; +or.nz.f0.0(16) null<1>UD g105<8,8,1>UD g103<8,8,1>UD { align1 1H @7 }; + +math cos(16) g17<1>F g15<8,8,1>F null<8,8,1>F { align1 1H @1 $0 }; +math exp(16) g1<1>F g29<8,8,1>F null<8,8,1>F { align1 1H @5 $2 }; +math sqrt(8) g9<1>HF g6<8,8,1>HF null<8,8,1>F { align1 1Q @1 $3 }; +math intdiv(8) g103<1>D g101<8,8,1>D g35<8,8,1>D { align1 1Q @4 $4 }; +math intmod(8) g101<1>D g97<8,8,1>D g76<8,8,1>D { align1 2Q @2 $5 }; +math inv(16) g10<1>F g8<8,8,1>F null<8,8,1>F { align1 2H @2 $6 }; +math log(16) g102<1>F g100<8,8,1>F null<8,8,1>F { align1 2H @1 $7 }; +math rsq(16) g76<1>F g74<8,8,1>F null<8,8,1>F { align1 1H @7 $8 }; +math sin(16) g123<1>F g121<8,8,1>F null<8,8,1>F { align1 1H @4 $9 }; +math sqrt(16) g43<1>F g47<8,8,1>F null<8,8,1>F { align1 2H @7 $10 }; +math cos(8) g103<1>HF g98<8,8,1>HF null<8,8,1>F { align1 1Q @3 $11 }; +math exp(8) g54<1>HF g52<8,8,1>HF null<8,8,1>F { align1 1Q @1 $12 }; +math intdiv(8) g35<1>D g31<8,8,1>D g33<8,8,1>D { align1 4Q @2 $13 }; +math intmod(8) g101<1>D g97<8,8,1>D g99<8,8,1>D { align1 2Q @4 $14 }; +math inv(8) g102<1>HF g92<8,8,1>HF null<8,8,1>F { align1 1Q @6 $15 }; + +sel.ge(16) g7<1>UW g7<16,16,1>UW g89<16,8,2>UW { align1 1H @7 $0.dst }; +mov(16) a0<1>UW 0x03e0UW { align1 WE_all 1H @3 $1.dst }; +add(16) g100<1>D g102<8,8,1>D -2114D { align1 1H @3 $2.dst }; +add(16) g100<1>D g105<8,8,1>D (abs)g18<8,8,1>D { align1 1H @3 $3.dst }; +add(16) g36<1>D g36<8,8,1>D g106<8,8,1>D { align1 1H @7 $4.dst }; +and(16) g49<1>UD g45<8,8,1>UD g47<8,8,1>UD { align1 1H @3 $5.dst }; +asr(16) g102<2>W g41<16,8,2>W g28<8,8,1>UD { align1 2H @6 $6.dst }; +cmp.l.f0.0(8) g97<1>F (abs)g96<8,8,1>F 0x3d4ccccdF /* 0.05F */ { align1 1Q @3 $7.dst }; +cmp.nz.f0.0(8) g100<1>F g98<8,8,1>F g99<8,8,1>F { align1 1Q @1 $8.dst }; +(+f0.0) sel(8) g64<1>D -g15<8,8,1>D g15<8,8,1>D { align1 1Q @1 $9.dst }; +mov(16) g15<1>UD g13<8,8,1>D { align1 1H @1 $10.dst }; +mul(8) acc0<1>UD g10<8,4,2>UD g101<16,8,2>UW { align1 1Q @7 $11.dst }; +or(16) g51<1>UW g51<16,16,1>UW g75<16,8,2>UW { align1 1H @7 $12.dst }; +sel.ge(16) g28<1>W g28<16,16,1>W g92<16,8,2>W { align1 2H @7 $13.dst }; +xor(16) g10<1>UD g10<8,8,1>UD g100<8,8,1>UD { align1 1H @7 $14.dst }; +and(16) g39<1>UD g35<8,8,1>UD g37<8,8,1>UD { align1 2H @5 $15.dst }; diff --git a/src/intel/tools/tests/gen12/swsb.expected b/src/intel/tools/tests/gen12/swsb.expected new file mode 100644 index 00000000000..223c3fecdd9 --- /dev/null +++ b/src/intel/tools/tests/gen12/swsb.expected @@ -0,0 +1,38 @@ +70 01 03 00 20 82 05 37 05 36 46 52 90 02 00 00 +61 02 24 00 60 05 05 06 05 14 46 00 00 00 00 00 +40 03 04 00 a0 0a 05 7a 05 62 46 0a 05 66 46 01 +69 04 03 00 60 86 05 4b 05 7a 46 02 02 00 00 00 +62 05 02 80 60 06 85 5a 64 5a 00 56 85 5a 34 00 +65 06 04 00 20 02 05 3a 05 10 46 02 05 38 46 00 +66 07 04 00 20 02 01 00 05 69 46 22 05 67 46 00 +38 90 04 00 a0 0a 05 11 05 0f 46 7a 01 00 46 00 +38 d2 04 00 a0 0a 05 01 05 1d 46 3a 01 00 46 00 +38 93 03 00 90 09 05 09 05 06 46 4a 01 00 46 00 +38 c4 03 00 60 06 05 67 05 65 46 c6 05 23 46 00 +38 a5 13 00 60 06 05 65 05 61 46 d6 05 4c 46 00 +38 a6 24 00 a0 0a 05 0a 05 08 46 1a 01 00 46 00 +38 97 24 00 a0 0a 05 66 05 64 46 2a 01 00 46 00 +38 f8 04 00 a0 0a 05 4c 05 4a 46 5a 01 00 46 00 +38 c9 04 00 a0 0a 05 7b 05 79 46 6a 01 00 46 00 +38 fa 24 00 a0 0a 05 2b 05 2f 46 4a 01 00 46 00 +38 bb 03 00 90 09 05 67 05 62 46 7a 01 00 46 00 +38 9c 03 00 90 09 05 36 05 34 46 3a 01 00 46 00 +38 ad 33 00 60 06 05 23 05 1f 46 c6 05 21 46 00 +38 ce 13 00 60 06 05 65 05 61 46 d6 05 63 46 00 +38 ef 03 00 90 09 05 66 05 5c 46 1a 01 00 46 00 +62 f0 04 00 10 01 05 07 05 07 58 41 06 59 56 00 +61 b1 04 80 10 41 01 10 00 00 00 00 e0 03 e0 03 +40 b2 04 00 60 86 05 64 05 66 46 06 be f7 ff ff +40 b3 04 00 60 06 05 64 05 69 46 06 05 12 46 01 +40 f4 04 00 60 06 05 24 05 24 46 06 05 6a 46 00 +65 b5 04 00 20 02 05 31 05 2d 46 02 05 2f 46 00 +6c e6 24 00 50 05 06 66 06 29 56 02 05 1c 46 00 +70 b7 03 00 a0 9a 05 61 05 60 46 5a cd cc 4c 3d +70 98 03 00 a0 0a 05 64 05 62 46 2a 05 63 46 00 +62 99 03 01 60 26 05 40 05 0f 46 06 05 0f 46 00 +61 9a 04 00 20 06 05 0f 05 0d 46 00 00 00 00 00 +41 fb 03 00 20 02 01 20 06 0a 44 01 06 65 56 00 +66 fc 04 00 10 01 05 33 05 33 58 01 06 4b 56 00 +62 fd 24 00 50 05 05 1c 05 1c 58 45 06 5c 56 00 +67 fe 04 00 20 02 05 0a 05 0a 46 02 05 64 46 00 +65 df 24 00 20 02 05 27 05 23 46 02 05 25 46 00 diff --git a/src/intel/tools/tests/gen12/sync.asm b/src/intel/tools/tests/gen12/sync.asm new file mode 100644 index 00000000000..a47c5dec28c --- /dev/null +++ b/src/intel/tools/tests/gen12/sync.asm @@ -0,0 +1,33 @@ +sync nop(16) null<0,1,0>UB { align1 WE_all 1H @1 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 1N @1 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 1N @2 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 1N @3 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 1N @4 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 1N @5 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 1N @6 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 1N @7 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 3N @1 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 3N @2 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 3N @3 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 3N @4 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 3N @5 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 3N @6 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 3N @7 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 5N @1 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 5N @2 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 5N @3 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 5N @4 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 5N @5 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 5N @6 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 5N @7 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 7N @1 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 7N @2 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 7N @3 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 7N @4 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 7N @5 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 7N @6 }; +sync nop(1) null<0,1,0>UB { align1 WE_all 7N @7 }; +sync nop(32) null<0,1,0>UB { align1 WE_all @1 }; +sync nop(8) null<0,1,0>UB { align1 WE_all 1Q @1 }; +sync allwr(16) null<0,1,0>UB { align1 1H }; +sync allwr(8) null<0,1,0>UB { align1 1Q }; diff --git a/src/intel/tools/tests/gen12/sync.expected b/src/intel/tools/tests/gen12/sync.expected new file mode 100644 index 00000000000..2e98e4ab791 --- /dev/null +++ b/src/intel/tools/tests/gen12/sync.expected @@ -0,0 +1,33 @@ +01 01 04 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 01 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 02 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 03 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 04 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 06 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 07 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 01 10 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 02 10 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 03 10 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 04 10 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 05 10 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 06 10 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 07 10 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 01 20 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 02 20 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 03 20 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 04 20 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 05 20 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 06 20 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 07 20 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 01 30 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 02 30 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 03 30 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 04 30 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 05 30 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 06 30 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 07 30 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 01 05 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 01 03 80 00 00 00 00 00 00 00 00 00 00 00 00 +01 00 04 00 00 00 00 00 00 00 00 30 00 00 00 00 +01 00 03 00 00 00 00 00 00 00 00 30 00 00 00 00
