Module: Mesa Branch: main Commit: 58d2a78dbaa7fe8f6d9dea85fa1cb2653a8cdf3e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=58d2a78dbaa7fe8f6d9dea85fa1cb2653a8cdf3e
Author: Samuel Pitoiset <samuel.pitoi...@gmail.com> Date: Tue Jan 9 08:59:21 2024 +0100 radv: move dri options to radv_instance::drirc To make it clearer that such an option is a per-application option. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26946> --- src/amd/vulkan/layers/radv_sqtt_layer.c | 2 +- .../vulkan/nir/radv_nir_apply_pipeline_layout.c | 2 +- src/amd/vulkan/radv_descriptor_set.c | 2 +- src/amd/vulkan/radv_device.c | 8 +- src/amd/vulkan/radv_device_memory.c | 2 +- src/amd/vulkan/radv_image.c | 2 +- src/amd/vulkan/radv_image_view.c | 2 +- src/amd/vulkan/radv_instance.c | 92 ++++++++++++---------- src/amd/vulkan/radv_physical_device.c | 32 ++++---- src/amd/vulkan/radv_pipeline.c | 14 ++-- src/amd/vulkan/radv_pipeline_compute.c | 2 +- src/amd/vulkan/radv_pipeline_graphics.c | 6 +- src/amd/vulkan/radv_pipeline_rt.c | 2 +- src/amd/vulkan/radv_private.h | 65 ++++++++------- src/amd/vulkan/radv_query.c | 6 +- src/amd/vulkan/radv_queue.c | 2 +- src/amd/vulkan/radv_sampler.c | 4 +- src/amd/vulkan/radv_shader.c | 4 +- src/amd/vulkan/radv_wsi.c | 2 +- 19 files changed, 128 insertions(+), 123 deletions(-) diff --git a/src/amd/vulkan/layers/radv_sqtt_layer.c b/src/amd/vulkan/layers/radv_sqtt_layer.c index a63080d9fb8..b946cb59658 100644 --- a/src/amd/vulkan/layers/radv_sqtt_layer.c +++ b/src/amd/vulkan/layers/radv_sqtt_layer.c @@ -338,7 +338,7 @@ radv_describe_begin_cmd_buffer(struct radv_cmd_buffer *cmd_buffer) if (cmd_buffer->qf == RADV_QUEUE_GENERAL) marker.queue_flags |= VK_QUEUE_GRAPHICS_BIT; - if (cmd_buffer->device->instance->legacy_sparse_binding) + if (cmd_buffer->device->instance->drirc.legacy_sparse_binding) marker.queue_flags |= VK_QUEUE_SPARSE_BINDING_BIT; radv_emit_sqtt_userdata(cmd_buffer, &marker, sizeof(marker) / 4); diff --git a/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c b/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c index 210a1357f00..7428b38eade 100644 --- a/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c +++ b/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c @@ -505,7 +505,7 @@ radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *device, c apply_layout_state state = { .gfx_level = device->physical_device->rad_info.gfx_level, .address32_hi = device->physical_device->rad_info.address32_hi, - .disable_aniso_single_level = device->instance->disable_aniso_single_level, + .disable_aniso_single_level = device->instance->drirc.disable_aniso_single_level, .has_image_load_dcc_bug = device->physical_device->rad_info.has_image_load_dcc_bug, .disable_tg4_trunc_coord = !device->physical_device->rad_info.conformant_trunc_coord && !device->disable_trunc_coord, diff --git a/src/amd/vulkan/radv_descriptor_set.c b/src/amd/vulkan/radv_descriptor_set.c index c9e68d8ddac..e0a4afa1de2 100644 --- a/src/amd/vulkan/radv_descriptor_set.c +++ b/src/amd/vulkan/radv_descriptor_set.c @@ -913,7 +913,7 @@ radv_create_descriptor_pool(struct radv_device *device, const VkDescriptorPoolCr if (!(pCreateInfo->flags & VK_DESCRIPTOR_POOL_CREATE_HOST_ONLY_BIT_EXT)) { enum radeon_bo_flag flags = RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT; - if (device->instance->zero_vram) + if (device->instance->drirc.zero_vram) flags |= RADEON_FLAG_ZERO_VRAM; VkResult result = device->ws->buffer_create(device->ws, bo_size, 32, RADEON_DOMAIN_VRAM, flags, diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index dd5ced88935..a7faa0bb8c6 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -595,11 +595,11 @@ init_dispatch_tables(struct radv_device *device, struct radv_physical_device *ph b.tables[RADV_RRA_DISPATCH_TABLE] = &device->layer_dispatch.rra; b.tables[RADV_RMV_DISPATCH_TABLE] = &device->layer_dispatch.rmv; - if (!strcmp(physical_device->instance->app_layer, "metroexodus")) { + if (!strcmp(physical_device->instance->drirc.app_layer, "metroexodus")) { add_entrypoints(&b, &metro_exodus_device_entrypoints, RADV_APP_DISPATCH_TABLE); - } else if (!strcmp(physical_device->instance->app_layer, "rage2")) { + } else if (!strcmp(physical_device->instance->drirc.app_layer, "rage2")) { add_entrypoints(&b, &rage2_device_entrypoints, RADV_APP_DISPATCH_TABLE); - } else if (!strcmp(physical_device->instance->app_layer, "quanticdream")) { + } else if (!strcmp(physical_device->instance->drirc.app_layer, "quanticdream")) { add_entrypoints(&b, &quantic_dream_device_entrypoints, RADV_APP_DISPATCH_TABLE); } @@ -1162,7 +1162,7 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n", 1 << util_logbase2(device->force_aniso)); } - device->disable_trunc_coord = device->instance->disable_trunc_coord; + device->disable_trunc_coord = device->instance->drirc.disable_trunc_coord; if (device->instance->vk.app_info.engine_name && !strcmp(device->instance->vk.app_info.engine_name, "DXVK")) { /* For DXVK 2.3.0 and older, use dualSrcBlend to determine if this is D3D9. */ diff --git a/src/amd/vulkan/radv_device_memory.c b/src/amd/vulkan/radv_device_memory.c index c6f5bf0b670..180583573da 100644 --- a/src/amd/vulkan/radv_device_memory.c +++ b/src/amd/vulkan/radv_device_memory.c @@ -224,7 +224,7 @@ radv_alloc_memory(struct radv_device *device, const VkMemoryAllocateInfo *pAlloc if (flags_info && flags_info->flags & VK_MEMORY_ALLOCATE_DEVICE_ADDRESS_CAPTURE_REPLAY_BIT) flags |= RADEON_FLAG_REPLAYABLE; - if (device->instance->zero_vram) + if (device->instance->drirc.zero_vram) flags |= RADEON_FLAG_ZERO_VRAM; if (device->overallocation_disallowed) { diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 3b8c7aec1dd..42f343491ae 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -1400,7 +1400,7 @@ radv_layout_is_htile_compressed(const struct radv_device *device, const struct r * the number of decompressions from/to GENERAL. */ if (radv_image_is_tc_compat_htile(image) && queue_mask & (1u << RADV_QUEUE_GENERAL) && - !device->instance->disable_tc_compat_htile_in_general) { + !device->instance->drirc.disable_tc_compat_htile_in_general) { return true; } else { return false; diff --git a/src/amd/vulkan/radv_image_view.c b/src/amd/vulkan/radv_image_view.c index 22a55c88aca..16049eb2243 100644 --- a/src/amd/vulkan/radv_image_view.c +++ b/src/amd/vulkan/radv_image_view.c @@ -504,7 +504,7 @@ gfx6_make_texture_descriptor(struct radv_device *device, struct radv_image *imag if (!(image->planes[0].surface.flags & RADEON_SURF_Z_OR_SBUFFER) && image->planes[0].surface.meta_offset) { state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format)); } else { - if (device->instance->disable_aniso_single_level) { + if (device->instance->drirc.disable_aniso_single_level) { /* The last dword is unused by hw. The shader uses it to clear * bits in the first dword of sampler state. */ diff --git a/src/amd/vulkan/radv_instance.c b/src/amd/vulkan/radv_instance.c index 71680241a44..6f47daba764 100644 --- a/src/amd/vulkan/radv_instance.c +++ b/src/amd/vulkan/radv_instance.c @@ -168,83 +168,89 @@ static const driOptionDescription radv_dri_options[] = { static void radv_init_dri_options(struct radv_instance *instance) { - driParseOptionInfo(&instance->available_dri_options, radv_dri_options, ARRAY_SIZE(radv_dri_options)); - driParseConfigFiles(&instance->dri_options, &instance->available_dri_options, 0, "radv", NULL, NULL, + driParseOptionInfo(&instance->drirc.available_options, radv_dri_options, ARRAY_SIZE(radv_dri_options)); + driParseConfigFiles(&instance->drirc.options, &instance->drirc.available_options, 0, "radv", NULL, NULL, instance->vk.app_info.app_name, instance->vk.app_info.app_version, instance->vk.app_info.engine_name, instance->vk.app_info.engine_version); - instance->enable_mrt_output_nan_fixup = driQueryOptionb(&instance->dri_options, "radv_enable_mrt_output_nan_fixup"); + instance->drirc.enable_mrt_output_nan_fixup = + driQueryOptionb(&instance->drirc.options, "radv_enable_mrt_output_nan_fixup"); - instance->disable_shrink_image_store = driQueryOptionb(&instance->dri_options, "radv_disable_shrink_image_store"); + instance->drirc.disable_shrink_image_store = + driQueryOptionb(&instance->drirc.options, "radv_disable_shrink_image_store"); - instance->disable_tc_compat_htile_in_general = - driQueryOptionb(&instance->dri_options, "radv_disable_tc_compat_htile_general"); + instance->drirc.disable_tc_compat_htile_in_general = + driQueryOptionb(&instance->drirc.options, "radv_disable_tc_compat_htile_general"); - if (driQueryOptionb(&instance->dri_options, "radv_no_dynamic_bounds")) + if (driQueryOptionb(&instance->drirc.options, "radv_no_dynamic_bounds")) instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS; - if (driQueryOptionb(&instance->dri_options, "radv_lower_discard_to_demote")) + if (driQueryOptionb(&instance->drirc.options, "radv_lower_discard_to_demote")) instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE; - if (driQueryOptionb(&instance->dri_options, "radv_invariant_geom")) + if (driQueryOptionb(&instance->drirc.options, "radv_invariant_geom")) instance->debug_flags |= RADV_DEBUG_INVARIANT_GEOM; - if (driQueryOptionb(&instance->dri_options, "radv_split_fma")) + if (driQueryOptionb(&instance->drirc.options, "radv_split_fma")) instance->debug_flags |= RADV_DEBUG_SPLIT_FMA; - if (driQueryOptionb(&instance->dri_options, "radv_disable_dcc")) + if (driQueryOptionb(&instance->drirc.options, "radv_disable_dcc")) instance->debug_flags |= RADV_DEBUG_NO_DCC; - instance->clear_lds = driQueryOptionb(&instance->dri_options, "radv_clear_lds"); + instance->drirc.clear_lds = driQueryOptionb(&instance->drirc.options, "radv_clear_lds"); - instance->zero_vram = driQueryOptionb(&instance->dri_options, "radv_zero_vram"); + instance->drirc.zero_vram = driQueryOptionb(&instance->drirc.options, "radv_zero_vram"); - instance->disable_aniso_single_level = driQueryOptionb(&instance->dri_options, "radv_disable_aniso_single_level"); + instance->drirc.disable_aniso_single_level = + driQueryOptionb(&instance->drirc.options, "radv_disable_aniso_single_level"); - instance->disable_trunc_coord = driQueryOptionb(&instance->dri_options, "radv_disable_trunc_coord"); + instance->drirc.disable_trunc_coord = driQueryOptionb(&instance->drirc.options, "radv_disable_trunc_coord"); - instance->disable_sinking_load_input_fs = - driQueryOptionb(&instance->dri_options, "radv_disable_sinking_load_input_fs"); + instance->drirc.disable_sinking_load_input_fs = + driQueryOptionb(&instance->drirc.options, "radv_disable_sinking_load_input_fs"); - instance->flush_before_query_copy = driQueryOptionb(&instance->dri_options, "radv_flush_before_query_copy"); + instance->drirc.flush_before_query_copy = driQueryOptionb(&instance->drirc.options, "radv_flush_before_query_copy"); - instance->enable_unified_heap_on_apu = driQueryOptionb(&instance->dri_options, "radv_enable_unified_heap_on_apu"); + instance->drirc.enable_unified_heap_on_apu = + driQueryOptionb(&instance->drirc.options, "radv_enable_unified_heap_on_apu"); - instance->tex_non_uniform = driQueryOptionb(&instance->dri_options, "radv_tex_non_uniform"); + instance->drirc.tex_non_uniform = driQueryOptionb(&instance->drirc.options, "radv_tex_non_uniform"); - instance->ssbo_non_uniform = driQueryOptionb(&instance->dri_options, "radv_ssbo_non_uniform"); + instance->drirc.ssbo_non_uniform = driQueryOptionb(&instance->drirc.options, "radv_ssbo_non_uniform"); - instance->app_layer = driQueryOptionstr(&instance->dri_options, "radv_app_layer"); + instance->drirc.app_layer = driQueryOptionstr(&instance->drirc.options, "radv_app_layer"); - instance->flush_before_timestamp_write = - driQueryOptionb(&instance->dri_options, "radv_flush_before_timestamp_write"); + instance->drirc.flush_before_timestamp_write = + driQueryOptionb(&instance->drirc.options, "radv_flush_before_timestamp_write"); - instance->force_rt_wave64 = driQueryOptionb(&instance->dri_options, "radv_rt_wave64"); + instance->drirc.force_rt_wave64 = driQueryOptionb(&instance->drirc.options, "radv_rt_wave64"); - instance->dual_color_blend_by_location = driQueryOptionb(&instance->dri_options, "dual_color_blend_by_location"); + instance->drirc.dual_color_blend_by_location = + driQueryOptionb(&instance->drirc.options, "dual_color_blend_by_location"); - instance->legacy_sparse_binding = driQueryOptionb(&instance->dri_options, "radv_legacy_sparse_binding"); + instance->drirc.legacy_sparse_binding = driQueryOptionb(&instance->drirc.options, "radv_legacy_sparse_binding"); - instance->override_graphics_shader_version = - driQueryOptioni(&instance->dri_options, "radv_override_graphics_shader_version"); - instance->override_compute_shader_version = - driQueryOptioni(&instance->dri_options, "radv_override_compute_shader_version"); - instance->override_ray_tracing_shader_version = - driQueryOptioni(&instance->dri_options, "radv_override_ray_tracing_shader_version"); + instance->drirc.override_graphics_shader_version = + driQueryOptioni(&instance->drirc.options, "radv_override_graphics_shader_version"); + instance->drirc.override_compute_shader_version = + driQueryOptioni(&instance->drirc.options, "radv_override_compute_shader_version"); + instance->drirc.override_ray_tracing_shader_version = + driQueryOptioni(&instance->drirc.options, "radv_override_ray_tracing_shader_version"); - instance->enable_dgc = driQueryOptionb(&instance->dri_options, "radv_dgc"); + instance->drirc.enable_dgc = driQueryOptionb(&instance->drirc.options, "radv_dgc"); - instance->override_vram_size = driQueryOptioni(&instance->dri_options, "override_vram_size"); + instance->drirc.override_vram_size = driQueryOptioni(&instance->drirc.options, "override_vram_size"); - instance->enable_khr_present_wait = driQueryOptionb(&instance->dri_options, "vk_khr_present_wait"); + instance->drirc.enable_khr_present_wait = driQueryOptionb(&instance->drirc.options, "vk_khr_present_wait"); - instance->override_uniform_offset_alignment = - driQueryOptioni(&instance->dri_options, "radv_override_uniform_offset_alignment"); + instance->drirc.override_uniform_offset_alignment = + driQueryOptioni(&instance->drirc.options, "radv_override_uniform_offset_alignment"); - instance->report_llvm9_version_string = driQueryOptionb(&instance->dri_options, "radv_report_llvm9_version_string"); + instance->drirc.report_llvm9_version_string = + driQueryOptionb(&instance->drirc.options, "radv_report_llvm9_version_string"); - instance->vk_require_etc2 = driQueryOptionb(&instance->dri_options, "vk_require_etc2"); - instance->vk_require_astc = driQueryOptionb(&instance->dri_options, "vk_require_astc"); + instance->drirc.vk_require_etc2 = driQueryOptionb(&instance->drirc.options, "vk_require_etc2"); + instance->drirc.vk_require_astc = driQueryOptionb(&instance->drirc.options, "vk_require_astc"); } static const struct vk_instance_extension_table radv_instance_extensions_supported = { @@ -359,8 +365,8 @@ radv_DestroyInstance(VkInstance _instance, const VkAllocationCallbacks *pAllocat VG(VALGRIND_DESTROY_MEMPOOL(instance)); - driDestroyOptionCache(&instance->dri_options); - driDestroyOptionInfo(&instance->available_dri_options); + driDestroyOptionCache(&instance->drirc.options); + driDestroyOptionInfo(&instance->drirc.available_options); vk_instance_finish(&instance->vk); vk_free(&instance->vk.alloc, instance); diff --git a/src/amd/vulkan/radv_physical_device.c b/src/amd/vulkan/radv_physical_device.c index d77a3d0f0c2..867a0956e46 100644 --- a/src/amd/vulkan/radv_physical_device.c +++ b/src/amd/vulkan/radv_physical_device.c @@ -224,7 +224,7 @@ enum radv_heap { static uint64_t radv_get_adjusted_vram_size(struct radv_physical_device *device) { - int ov = device->instance->override_vram_size; + int ov = device->instance->drirc.override_vram_size; if (ov >= 0) return MIN2((uint64_t)device->rad_info.vram_size_kb * 1024, (uint64_t)ov << 20); return (uint64_t)device->rad_info.vram_size_kb * 1024; @@ -257,7 +257,7 @@ radv_physical_device_init_mem_types(struct radv_physical_device *device) if (!device->rad_info.has_dedicated_vram) { const uint64_t total_size = gtt_size + visible_vram_size; - if (device->instance->enable_unified_heap_on_apu) { + if (device->instance->drirc.enable_unified_heap_on_apu) { /* Some applications seem better when the driver exposes only one heap of VRAM on APUs. */ visible_vram_size = total_size; gtt_size = 0; @@ -475,9 +475,9 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device * but the feature is useful enough to hide behind an opt-in mechanism for now. * If the instance only enables surface extensions that unconditionally support present wait, * we can also expose the extension that way. */ - .KHR_present_id = device->instance->enable_khr_present_wait || + .KHR_present_id = device->instance->drirc.enable_khr_present_wait || wsi_common_vk_instance_supports_present_wait(&device->instance->vk), - .KHR_present_wait = device->instance->enable_khr_present_wait || + .KHR_present_wait = device->instance->drirc.enable_khr_present_wait || wsi_common_vk_instance_supports_present_wait(&device->instance->vk), .KHR_push_descriptor = true, .KHR_ray_query = radv_enable_rt(device, false), @@ -603,7 +603,7 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device .EXT_tooling_info = true, .EXT_transform_feedback = true, .EXT_vertex_attribute_divisor = true, - .EXT_vertex_input_dynamic_state = !device->use_llvm && !device->instance->enable_dgc, + .EXT_vertex_input_dynamic_state = !device->use_llvm && !device->instance->drirc.enable_dgc, .EXT_ycbcr_image_arrays = true, .AMD_buffer_marker = true, .AMD_device_coherent_memory = true, @@ -632,8 +632,8 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device .GOOGLE_user_type = true, .INTEL_shader_integer_functions2 = true, .NV_compute_shader_derivatives = true, - .NV_device_generated_commands = device->instance->enable_dgc, - .NV_device_generated_commands_compute = device->instance->enable_dgc, + .NV_device_generated_commands = device->instance->drirc.enable_dgc, + .NV_device_generated_commands_compute = device->instance->drirc.enable_dgc, /* Undocumented extension purely for vkd3d-proton. This check is to prevent anyone else from * using it. */ @@ -1132,7 +1132,7 @@ radv_max_descriptor_set_size() static uint32_t radv_uniform_buffer_offset_alignment(const struct radv_physical_device *pdevice) { - uint32_t uniform_offset_alignment = pdevice->instance->override_uniform_offset_alignment; + uint32_t uniform_offset_alignment = pdevice->instance->drirc.override_uniform_offset_alignment; if (!util_is_power_of_two_or_zero(uniform_offset_alignment)) { fprintf(stderr, "ERROR: invalid radv_override_uniform_offset_alignment setting %d:" @@ -1153,7 +1153,7 @@ radv_get_compiler_string(struct radv_physical_device *pdevice) * version is too old or if the LLVM version string is * missing. This gives 2-5% performance with SotTR and ACO. */ - if (pdevice->instance->report_llvm9_version_string) { + if (pdevice->instance->drirc.report_llvm9_version_string) { return " (LLVM 9.0.1)"; } @@ -1907,8 +1907,8 @@ radv_physical_device_try_create(struct radv_instance *instance, drmDevicePtr drm device->emulate_etc2 = !radv_device_supports_etc(device); device->emulate_astc = true; #else - device->emulate_etc2 = !radv_device_supports_etc(device) && instance->vk_require_etc2; - device->emulate_astc = instance->vk_require_astc; + device->emulate_etc2 = !radv_device_supports_etc(device) && instance->drirc.vk_require_etc2; + device->emulate_astc = instance->drirc.vk_require_astc; #endif snprintf(device->name, sizeof(device->name), "AMD RADV %s%s", device->rad_info.name, @@ -1978,8 +1978,8 @@ radv_physical_device_try_create(struct radv_instance *instance, drmDevicePtr drm * dependence wave32 would likely be a net-loss (as well as the SALU count becoming more * problematic) */ - if (!(device->instance->perftest_flags & RADV_PERFTEST_RT_WAVE_64) && !(device->instance->force_rt_wave64) && - device->rad_info.gfx_level < GFX11) + if (!(device->instance->perftest_flags & RADV_PERFTEST_RT_WAVE_64) && + !(device->instance->drirc.force_rt_wave64) && device->rad_info.gfx_level < GFX11) device->rt_wave_size = 32; } @@ -2142,7 +2142,7 @@ radv_get_physical_device_queue_family_properties(struct radv_physical_device *pd idx = 0; if (*pCount >= 1) { VkQueueFlags gfx_flags = VK_QUEUE_GRAPHICS_BIT | VK_QUEUE_COMPUTE_BIT | VK_QUEUE_TRANSFER_BIT; - if (pdevice->instance->legacy_sparse_binding) + if (pdevice->instance->drirc.legacy_sparse_binding) gfx_flags |= VK_QUEUE_SPARSE_BINDING_BIT; *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties){ .queueFlags = gfx_flags, @@ -2156,7 +2156,7 @@ radv_get_physical_device_queue_family_properties(struct radv_physical_device *pd if (pdevice->rad_info.ip[AMD_IP_COMPUTE].num_queues > 0 && !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) { VkQueueFlags compute_flags = VK_QUEUE_COMPUTE_BIT | VK_QUEUE_TRANSFER_BIT; - if (pdevice->instance->legacy_sparse_binding) + if (pdevice->instance->drirc.legacy_sparse_binding) compute_flags |= VK_QUEUE_SPARSE_BINDING_BIT; if (*pCount > idx) { *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties){ @@ -2278,7 +2278,7 @@ radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice, * in presence of shared buffers). */ if (!device->rad_info.has_dedicated_vram) { - if (device->instance->enable_unified_heap_on_apu) { + if (device->instance->drirc.enable_unified_heap_on_apu) { /* When the heaps are unified, only the visible VRAM heap is exposed on APUs. */ assert(device->heaps == RADV_HEAP_VRAM_VIS); assert(device->memory_properties.memoryHeaps[0].flags == VK_MEMORY_HEAP_DEVICE_LOCAL_BIT); diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index c46360ac69d..65720935aa8 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -155,14 +155,14 @@ radv_generate_pipeline_key(const struct radv_device *device, const VkPipelineSha key.optimisations_disabled = 1; key.disable_aniso_single_level = - device->instance->disable_aniso_single_level && device->physical_device->rad_info.gfx_level < GFX8; + device->instance->drirc.disable_aniso_single_level && device->physical_device->rad_info.gfx_level < GFX8; key.disable_trunc_coord = device->disable_trunc_coord; key.image_2d_view_of_3d = device->image_2d_view_of_3d && device->physical_device->rad_info.gfx_level == GFX9; - key.tex_non_uniform = device->instance->tex_non_uniform; - key.ssbo_non_uniform = device->instance->ssbo_non_uniform; + key.tex_non_uniform = device->instance->drirc.tex_non_uniform; + key.ssbo_non_uniform = device->instance->drirc.ssbo_non_uniform; for (unsigned i = 0; i < num_stages; ++i) { const VkPipelineShaderStageCreateInfo *const stage = &stages[i]; @@ -266,9 +266,9 @@ radv_get_hash_flags(const struct radv_device *device, bool stats) hash_flags |= RADV_HASH_SHADER_NO_FMASK; if (device->instance->debug_flags & RADV_DEBUG_NO_RT) hash_flags |= RADV_HASH_SHADER_NO_RT; - if (device->instance->dual_color_blend_by_location) + if (device->instance->drirc.dual_color_blend_by_location) hash_flags |= RADV_HASH_SHADER_DUAL_BLEND_MRT1; - if (device->instance->clear_lds) + if (device->instance->drirc.clear_lds) hash_flags |= RADV_HASH_SHADER_CLEAR_LDS; return hash_flags; } @@ -582,7 +582,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_key NIR_PASS(progress, stage->nir, nir_opt_load_store_vectorize, &vectorize_opts); if (progress) { NIR_PASS(_, stage->nir, nir_copy_prop); - NIR_PASS(_, stage->nir, nir_opt_shrink_stores, !device->instance->disable_shrink_image_store); + NIR_PASS(_, stage->nir, nir_opt_shrink_stores, !device->instance->drirc.disable_shrink_image_store); /* Gather info again, to update whether 8/16-bit are used. */ nir_shader_gather_info(stage->nir, nir_shader_get_entrypoint(stage->nir)); @@ -796,7 +796,7 @@ radv_shader_should_clear_lds(const struct radv_device *device, const nir_shader { return (shader->info.stage == MESA_SHADER_COMPUTE || shader->info.stage == MESA_SHADER_MESH || shader->info.stage == MESA_SHADER_TASK) && - shader->info.shared_size > 0 && device->instance->clear_lds; + shader->info.shared_size > 0 && device->instance->drirc.clear_lds; } static uint32_t diff --git a/src/amd/vulkan/radv_pipeline_compute.c b/src/amd/vulkan/radv_pipeline_compute.c index a3bbb92b58a..edc14e6130c 100644 --- a/src/amd/vulkan/radv_pipeline_compute.c +++ b/src/amd/vulkan/radv_pipeline_compute.c @@ -112,7 +112,7 @@ radv_generate_compute_pipeline_key(const struct radv_device *device, const struc struct radv_pipeline_key key = radv_generate_pipeline_key(device, &pCreateInfo->stage, 1, pipeline->base.create_flags, pCreateInfo->pNext); - key.shader_version = device->instance->override_compute_shader_version; + key.shader_version = device->instance->drirc.override_compute_shader_version; return key; } diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index bc693edbf97..ddebb2d3b7e 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -1725,7 +1725,7 @@ radv_generate_ps_epilog_key(const struct radv_device *device, const struct radv_ key.spi_shader_col_format = col_format; key.color_is_int8 = device->physical_device->rad_info.gfx_level < GFX8 ? is_int8 : 0; key.color_is_int10 = device->physical_device->rad_info.gfx_level < GFX8 ? is_int10 : 0; - key.enable_mrt_output_nan_fixup = device->instance->enable_mrt_output_nan_fixup ? is_float32 : 0; + key.enable_mrt_output_nan_fixup = device->instance->drirc.enable_mrt_output_nan_fixup ? is_float32 : 0; key.mrt0_is_dual_src = state->mrt0_is_dual_src; key.export_depth = state->export_depth; key.export_stencil = state->export_stencil; @@ -1803,7 +1803,7 @@ radv_generate_graphics_pipeline_key(const struct radv_device *device, const stru struct radv_pipeline_key key = radv_generate_pipeline_key(device, pCreateInfo->pStages, pCreateInfo->stageCount, pipeline->base.create_flags, pCreateInfo->pNext); - key.shader_version = device->instance->override_graphics_shader_version; + key.shader_version = device->instance->drirc.override_graphics_shader_version; key.lib_flags = lib_flags; key.has_multiview_view_index = state->rp ? !!state->rp->view_mask : 0; @@ -1908,7 +1908,7 @@ radv_generate_graphics_pipeline_key(const struct radv_device *device, const stru device->physical_device->rad_info.family == CHIP_VANGOGH)) key.adjust_frag_coord_z = true; - if (device->instance->disable_sinking_load_input_fs) + if (device->instance->drirc.disable_sinking_load_input_fs) key.disable_sinking_load_input_fs = true; if (device->primitives_generated_query) diff --git a/src/amd/vulkan/radv_pipeline_rt.c b/src/amd/vulkan/radv_pipeline_rt.c index 91f579cac7e..c4ca2a2126b 100644 --- a/src/amd/vulkan/radv_pipeline_rt.c +++ b/src/amd/vulkan/radv_pipeline_rt.c @@ -91,7 +91,7 @@ radv_generate_rt_pipeline_key(const struct radv_device *device, const struct rad struct radv_pipeline_key key = radv_generate_pipeline_key(device, pCreateInfo->pStages, pCreateInfo->stageCount, pipeline->base.base.create_flags, pCreateInfo->pNext); - key.shader_version = device->instance->override_ray_tracing_shader_version; + key.shader_version = device->instance->drirc.override_ray_tracing_shader_version; if (pCreateInfo->pLibraryInfo) { for (unsigned i = 0; i < pCreateInfo->pLibraryInfo->libraryCount; ++i) { diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 3e704256c5d..7aea07f3fe7 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -361,39 +361,38 @@ struct radv_instance { uint64_t debug_flags; uint64_t perftest_flags; - struct driOptionCache dri_options; - struct driOptionCache available_dri_options; - - /** - * Workarounds for game bugs. - */ - bool enable_mrt_output_nan_fixup; - bool disable_tc_compat_htile_in_general; - bool disable_shrink_image_store; - bool disable_aniso_single_level; - bool disable_trunc_coord; - bool zero_vram; - bool disable_sinking_load_input_fs; - bool flush_before_query_copy; - bool enable_unified_heap_on_apu; - bool tex_non_uniform; - bool ssbo_non_uniform; - bool flush_before_timestamp_write; - bool force_rt_wave64; - bool dual_color_blend_by_location; - bool legacy_sparse_binding; - bool clear_lds; - bool enable_dgc; - bool enable_khr_present_wait; - bool report_llvm9_version_string; - bool vk_require_etc2; - bool vk_require_astc; - char *app_layer; - uint8_t override_graphics_shader_version; - uint8_t override_compute_shader_version; - uint8_t override_ray_tracing_shader_version; - int override_vram_size; - int override_uniform_offset_alignment; + struct { + struct driOptionCache options; + struct driOptionCache available_options; + + bool enable_mrt_output_nan_fixup; + bool disable_tc_compat_htile_in_general; + bool disable_shrink_image_store; + bool disable_aniso_single_level; + bool disable_trunc_coord; + bool zero_vram; + bool disable_sinking_load_input_fs; + bool flush_before_query_copy; + bool enable_unified_heap_on_apu; + bool tex_non_uniform; + bool ssbo_non_uniform; + bool flush_before_timestamp_write; + bool force_rt_wave64; + bool dual_color_blend_by_location; + bool legacy_sparse_binding; + bool clear_lds; + bool enable_dgc; + bool enable_khr_present_wait; + bool report_llvm9_version_string; + bool vk_require_etc2; + bool vk_require_astc; + char *app_layer; + uint8_t override_graphics_shader_version; + uint8_t override_compute_shader_version; + uint8_t override_ray_tracing_shader_version; + int override_vram_size; + int override_uniform_offset_alignment; + } drirc; }; VkResult radv_init_wsi(struct radv_physical_device *physical_device); diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index 17da2892d3d..0a215ba761d 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -1682,7 +1682,7 @@ radv_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPoo /* Workaround engines that forget to properly specify WAIT_BIT because some driver implicitly * synchronizes before query copy. */ - if (cmd_buffer->device->instance->flush_before_query_copy) + if (cmd_buffer->device->instance->drirc.flush_before_query_copy) cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits; /* From the Vulkan spec 1.1.108: @@ -2452,7 +2452,7 @@ radv_CmdWriteTimestamp2(VkCommandBuffer commandBuffer, VkPipelineStageFlags2 sta radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo); if (cmd_buffer->qf == RADV_QUEUE_TRANSFER) { - if (cmd_buffer->device->instance->flush_before_timestamp_write) { + if (cmd_buffer->device->instance->drirc.flush_before_timestamp_write) { radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 1); radeon_emit(cmd_buffer->cs, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); } @@ -2466,7 +2466,7 @@ radv_CmdWriteTimestamp2(VkCommandBuffer commandBuffer, VkPipelineStageFlags2 sta return; } - if (cmd_buffer->device->instance->flush_before_timestamp_write) { + if (cmd_buffer->device->instance->drirc.flush_before_timestamp_write) { /* Make sure previously launched waves have finished */ cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_CS_PARTIAL_FLUSH; } diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index 92494088606..3d4382878d1 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -1728,7 +1728,7 @@ radv_queue_submit(struct vk_queue *vqueue, struct vk_queue_submit *submission) struct radv_queue *queue = (struct radv_queue *)vqueue; VkResult result; - if (queue->device->instance->legacy_sparse_binding) { + if (queue->device->instance->drirc.legacy_sparse_binding) { result = radv_queue_submit_bind_sparse_memory(queue->device, submission); if (result != VK_SUCCESS) goto fail; diff --git a/src/amd/vulkan/radv_sampler.c b/src/amd/vulkan/radv_sampler.c index baf171dd5f7..d7e10280fff 100644 --- a/src/amd/vulkan/radv_sampler.c +++ b/src/amd/vulkan/radv_sampler.c @@ -246,12 +246,12 @@ radv_init_sampler(struct radv_device *device, struct radv_sampler *sampler, cons if (device->physical_device->rad_info.gfx_level >= GFX10) { sampler->state[2] |= S_008F38_LOD_BIAS(radv_float_to_sfixed(CLAMP(pCreateInfo->mipLodBias, -32, 31), 8)) | - S_008F38_ANISO_OVERRIDE_GFX10(device->instance->disable_aniso_single_level); + S_008F38_ANISO_OVERRIDE_GFX10(device->instance->drirc.disable_aniso_single_level); } else { sampler->state[2] |= S_008F38_LOD_BIAS(radv_float_to_sfixed(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) | S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.gfx_level <= GFX8) | S_008F38_FILTER_PREC_FIX(1) | - S_008F38_ANISO_OVERRIDE_GFX8(device->instance->disable_aniso_single_level && + S_008F38_ANISO_OVERRIDE_GFX8(device->instance->drirc.disable_aniso_single_level && device->physical_device->rad_info.gfx_level >= GFX8); } diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index a762fd5690d..30c1679afba 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -542,7 +542,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared, &dead_vars_opts); if (nir->info.stage == MESA_SHADER_FRAGMENT && key->ps.epilog.mrt0_is_dual_src && - device->instance->dual_color_blend_by_location) + device->instance->drirc.dual_color_blend_by_location) fix_dual_src_mrt1_export(nir); /* Variables can make nir_propagate_invariant more conservative @@ -668,7 +668,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st }); NIR_PASS(_, nir, nir_lower_load_const_to_scalar); - NIR_PASS(_, nir, nir_opt_shrink_stores, !device->instance->disable_shrink_image_store); + NIR_PASS(_, nir, nir_opt_shrink_stores, !device->instance->drirc.disable_shrink_image_store); if (!key->optimisations_disabled) radv_optimize_nir(nir, false); diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c index f8c339bd210..1c9033fdfc9 100644 --- a/src/amd/vulkan/radv_wsi.c +++ b/src/amd/vulkan/radv_wsi.c @@ -92,7 +92,7 @@ radv_init_wsi(struct radv_physical_device *physical_device) VkResult result = wsi_device_init(&physical_device->wsi_device, radv_physical_device_to_handle(physical_device), radv_wsi_proc_addr, &physical_device->instance->vk.alloc, physical_device->master_fd, - &physical_device->instance->dri_options, &(struct wsi_device_options){.sw_device = false}); + &physical_device->instance->drirc.options, &(struct wsi_device_options){.sw_device = false}); if (result != VK_SUCCESS) return result;
