Module: Mesa Branch: main Commit: 7f39e51dd5144b95844b4226f83346bbf84f1f87 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f39e51dd5144b95844b4226f83346bbf84f1f87
Author: Francisco Jerez <curroje...@riseup.net> Date: Mon Mar 7 16:28:28 2022 -0800 intel/compiler/xe2: Add extra flag registers. Reviewed-by: Caio Oliveira <caio.olive...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860> --- src/intel/compiler/brw_ir.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_ir.h b/src/intel/compiler/brw_ir.h index e7f54798303..3b4b19c244a 100644 --- a/src/intel/compiler/brw_ir.h +++ b/src/intel/compiler/brw_ir.h @@ -194,10 +194,10 @@ struct backend_instruction { */ bool eot:1; - /* Chooses which flag subregister (f0.0 to f1.1) is used for conditional + /* Chooses which flag subregister (f0.0 to f3.1) is used for conditional * mod and predication. */ - unsigned flag_subreg:2; + unsigned flag_subreg:3; /** * Systolic depth used by DPAS instruction.
