Module: Mesa Branch: main Commit: fb80421a62356c3c8af6f868dc4f690b59efb33b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb80421a62356c3c8af6f868dc4f690b59efb33b
Author: Samuel Pitoiset <samuel.pitoi...@gmail.com> Date: Thu Jan 11 16:20:06 2024 +0100 radv: stop passing the pipeline key when compiling compute/rt shaders The pipeline key now essentially contains graphics state. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27007> --- src/amd/vulkan/nir/radv_nir_rt_shader.c | 2 +- src/amd/vulkan/radv_pipeline_compute.c | 24 +++++++++++------------- src/amd/vulkan/radv_pipeline_rt.c | 23 +++++++++++------------ 3 files changed, 23 insertions(+), 26 deletions(-) diff --git a/src/amd/vulkan/nir/radv_nir_rt_shader.c b/src/amd/vulkan/nir/radv_nir_rt_shader.c index 8a8b3a08236..9fb0b25abda 100644 --- a/src/amd/vulkan/nir/radv_nir_rt_shader.c +++ b/src/amd/vulkan/nir/radv_nir_rt_shader.c @@ -815,7 +815,7 @@ radv_parse_rt_stage(struct radv_device *device, const VkPipelineShaderStageCreat radv_pipeline_stage_init(sinfo, pipeline_layout, key, &rt_stage); - nir_shader *shader = radv_shader_spirv_to_nir(device, &rt_stage, key, false); + nir_shader *shader = radv_shader_spirv_to_nir(device, &rt_stage, NULL, false); NIR_PASS(_, shader, nir_lower_vars_to_explicit_types, nir_var_function_temp | nir_var_shader_call_data, glsl_get_natural_size_align_bytes); diff --git a/src/amd/vulkan/radv_pipeline_compute.c b/src/amd/vulkan/radv_pipeline_compute.c index 1c4bf9d4946..6d3ace8c13e 100644 --- a/src/amd/vulkan/radv_pipeline_compute.c +++ b/src/amd/vulkan/radv_pipeline_compute.c @@ -133,13 +133,13 @@ radv_compute_pipeline_init(const struct radv_device *device, struct radv_compute static struct radv_shader * radv_compile_cs(struct radv_device *device, struct vk_pipeline_cache *cache, struct radv_shader_stage *cs_stage, - const struct radv_pipeline_key *pipeline_key, bool keep_executable_info, bool keep_statistic_info, - bool is_internal, struct radv_shader_binary **cs_binary) + bool keep_executable_info, bool keep_statistic_info, bool is_internal, + struct radv_shader_binary **cs_binary) { struct radv_shader *cs_shader; /* Compile SPIR-V shader to NIR. */ - cs_stage->nir = radv_shader_spirv_to_nir(device, cs_stage, pipeline_key, is_internal); + cs_stage->nir = radv_shader_spirv_to_nir(device, cs_stage, NULL, is_internal); radv_optimize_nir(cs_stage->nir, cs_stage->key.optimisations_disabled); @@ -148,17 +148,16 @@ radv_compile_cs(struct radv_device *device, struct vk_pipeline_cache *cache, str /* Run the shader info pass. */ radv_nir_shader_info_init(cs_stage->stage, MESA_SHADER_NONE, &cs_stage->info); - radv_nir_shader_info_pass(device, cs_stage->nir, &cs_stage->layout, &cs_stage->key, pipeline_key, - RADV_PIPELINE_COMPUTE, false, &cs_stage->info); + radv_nir_shader_info_pass(device, cs_stage->nir, &cs_stage->layout, &cs_stage->key, NULL, RADV_PIPELINE_COMPUTE, + false, &cs_stage->info); - radv_declare_shader_args(device, pipeline_key, &cs_stage->info, MESA_SHADER_COMPUTE, MESA_SHADER_NONE, - &cs_stage->args); + radv_declare_shader_args(device, NULL, &cs_stage->info, MESA_SHADER_COMPUTE, MESA_SHADER_NONE, &cs_stage->args); cs_stage->info.user_sgprs_locs = cs_stage->args.user_sgprs_locs; cs_stage->info.inline_push_constant_mask = cs_stage->args.ac.inline_push_const_mask; /* Postprocess NIR. */ - radv_postprocess_nir(device, pipeline_key, cs_stage); + radv_postprocess_nir(device, NULL, cs_stage); if (radv_can_dump_shader(device, cs_stage->nir, false)) nir_print_shader(cs_stage->nir, stderr); @@ -166,8 +165,8 @@ radv_compile_cs(struct radv_device *device, struct vk_pipeline_cache *cache, str /* Compile NIR shader to AMD assembly. */ bool dump_shader = radv_can_dump_shader(device, cs_stage->nir, false); - *cs_binary = radv_shader_nir_to_asm(device, cs_stage, &cs_stage->nir, 1, pipeline_key, keep_executable_info, - keep_statistic_info); + *cs_binary = + radv_shader_nir_to_asm(device, cs_stage, &cs_stage->nir, 1, NULL, keep_executable_info, keep_statistic_info); cs_shader = radv_shader_create(device, cache, *cs_binary, keep_executable_info || dump_shader); @@ -222,9 +221,8 @@ radv_compute_pipeline_compile(struct radv_compute_pipeline *pipeline, struct rad int64_t stage_start = os_time_get_nano(); - pipeline->base.shaders[MESA_SHADER_COMPUTE] = - radv_compile_cs(device, cache, &cs_stage, pipeline_key, keep_executable_info, keep_statistic_info, - pipeline->base.is_internal, &cs_binary); + pipeline->base.shaders[MESA_SHADER_COMPUTE] = radv_compile_cs( + device, cache, &cs_stage, keep_executable_info, keep_statistic_info, pipeline->base.is_internal, &cs_binary); cs_stage.feedback.duration += os_time_get_nano() - stage_start; diff --git a/src/amd/vulkan/radv_pipeline_rt.c b/src/amd/vulkan/radv_pipeline_rt.c index cc148bda580..b9210509920 100644 --- a/src/amd/vulkan/radv_pipeline_rt.c +++ b/src/amd/vulkan/radv_pipeline_rt.c @@ -357,10 +357,9 @@ move_rt_instructions(nir_shader *shader) static VkResult radv_rt_nir_to_asm(struct radv_device *device, struct vk_pipeline_cache *cache, - const VkRayTracingPipelineCreateInfoKHR *pCreateInfo, const struct radv_pipeline_key *pipeline_key, - struct radv_ray_tracing_pipeline *pipeline, bool monolithic, struct radv_shader_stage *stage, - uint32_t *stack_size, struct radv_serialized_shader_arena_block *replay_block, - struct radv_shader **out_shader) + const VkRayTracingPipelineCreateInfoKHR *pCreateInfo, struct radv_ray_tracing_pipeline *pipeline, + bool monolithic, struct radv_shader_stage *stage, uint32_t *stack_size, + struct radv_serialized_shader_arena_block *replay_block, struct radv_shader **out_shader) { struct radv_shader_binary *binary; bool keep_executable_info = radv_pipeline_capture_shaders(device, pipeline->base.base.create_flags); @@ -369,11 +368,11 @@ radv_rt_nir_to_asm(struct radv_device *device, struct vk_pipeline_cache *cache, /* Gather shader info. */ nir_shader_gather_info(stage->nir, nir_shader_get_entrypoint(stage->nir)); radv_nir_shader_info_init(stage->stage, MESA_SHADER_NONE, &stage->info); - radv_nir_shader_info_pass(device, stage->nir, &stage->layout, &stage->key, pipeline_key, RADV_PIPELINE_RAY_TRACING, - false, &stage->info); + radv_nir_shader_info_pass(device, stage->nir, &stage->layout, &stage->key, NULL, RADV_PIPELINE_RAY_TRACING, false, + &stage->info); /* Declare shader arguments. */ - radv_declare_shader_args(device, pipeline_key, &stage->info, stage->stage, MESA_SHADER_NONE, &stage->args); + radv_declare_shader_args(device, NULL, &stage->info, stage->stage, MESA_SHADER_NONE, &stage->args); stage->info.user_sgprs_locs = stage->args.user_sgprs_locs; stage->info.inline_push_constant_mask = stage->args.ac.inline_push_const_mask; @@ -416,7 +415,7 @@ radv_rt_nir_to_asm(struct radv_device *device, struct vk_pipeline_cache *cache, radv_nir_lower_rt_abi(temp_stage.nir, pCreateInfo, &temp_stage.args, &stage->info, stack_size, i > 0, device, pipeline, monolithic); radv_optimize_nir(temp_stage.nir, stage->key.optimisations_disabled); - radv_postprocess_nir(device, pipeline_key, &temp_stage); + radv_postprocess_nir(device, NULL, &temp_stage); if (radv_can_dump_shader(device, temp_stage.nir, false)) nir_print_shader(temp_stage.nir, stderr); @@ -427,8 +426,8 @@ radv_rt_nir_to_asm(struct radv_device *device, struct vk_pipeline_cache *cache, pipeline->base.base.create_flags & VK_PIPELINE_CREATE_2_RAY_TRACING_SHADER_GROUP_HANDLE_CAPTURE_REPLAY_BIT_KHR; /* Compile NIR shader to AMD assembly. */ - binary = radv_shader_nir_to_asm(device, stage, shaders, num_shaders, pipeline_key, keep_executable_info, - keep_statistic_info); + binary = + radv_shader_nir_to_asm(device, stage, shaders, num_shaders, NULL, keep_executable_info, keep_statistic_info); struct radv_shader *shader; if (replay_block || replayable) { VkResult result = radv_shader_create_uncached(device, binary, replayable, replay_block, &shader); @@ -584,7 +583,7 @@ radv_rt_compile_shaders(struct radv_device *device, struct vk_pipeline_cache *ca bool monolithic_raygen = monolithic && stage->stage == MESA_SHADER_RAYGEN; - result = radv_rt_nir_to_asm(device, cache, pCreateInfo, key, pipeline, monolithic_raygen, stage, &stack_size, + result = radv_rt_nir_to_asm(device, cache, pCreateInfo, pipeline, monolithic_raygen, stage, &stack_size, replay_block, &rt_stages[idx].shader); if (result != VK_SUCCESS) goto cleanup; @@ -625,7 +624,7 @@ radv_rt_compile_shaders(struct radv_device *device, struct vk_pipeline_cache *ca vk_pipeline_hash_shader_stage(&pStage, NULL, traversal_stage.shader_sha1); radv_shader_layout_init(pipeline_layout, MESA_SHADER_INTERSECTION, &traversal_stage.layout); radv_shader_stage_key_init(key, MESA_SHADER_INTERSECTION, &traversal_stage.key); - result = radv_rt_nir_to_asm(device, cache, pCreateInfo, key, pipeline, false, &traversal_stage, NULL, NULL, + result = radv_rt_nir_to_asm(device, cache, pCreateInfo, pipeline, false, &traversal_stage, NULL, NULL, &pipeline->base.base.shaders[MESA_SHADER_INTERSECTION]); ralloc_free(traversal_module.nir);
