Module: Mesa
Branch: master
Commit: 05d1d86907b12011fdb80e147ae68b4cd207f789
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=05d1d86907b12011fdb80e147ae68b4cd207f789

Author: Dave Airlie <[email protected]>
Date:   Fri Oct  1 09:43:14 2010 +1000

r600g: add winsys support for CTL constants.

These need to be emitted, we also need them to do proper vtx start,
instead of abusing index offset.

---

 src/gallium/drivers/r600/evergreen_state.c         |    2 ++
 src/gallium/drivers/r600/evergreend.h              |    6 ++++++
 src/gallium/drivers/r600/r600_state.c              |    2 ++
 src/gallium/drivers/r600/r600d.h                   |    3 +++
 src/gallium/winsys/r600/drm/evergreen_hw_context.c |   10 ++++++++++
 src/gallium/winsys/r600/drm/r600_hw_context.c      |    9 +++++++++
 src/gallium/winsys/r600/drm/r600d.h                |    3 +++
 7 files changed, 35 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 5775b04..21d3394 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1450,6 +1450,8 @@ void evergreen_draw(struct pipe_context *ctx, const 
struct pipe_draw_info *info)
        r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, 
rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, 
draw.max_index, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, 
draw.min_index, 0xFFFFFFFF, NULL);
+       r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 
0xFFFFFFFF, NULL);
+       r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 
0xFFFFFFFF, NULL);
 
        if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
                float offset_units = rctx->rasterizer->offset_units;
diff --git a/src/gallium/drivers/r600/evergreend.h 
b/src/gallium/drivers/r600/evergreend.h
index 54b26f6..ce2b667 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -40,6 +40,9 @@
 #define EVERGREEN_SAMPLER_OFFSET                    0X0003C000
 #define EVERGREEN_SAMPLER_END                       0X0003CFF0
 
+#define EVERGREEN_CTL_CONST_OFFSET                  0x0003CFF0
+#define EVERGREEN_CTL_CONST_END                     0x0003E200
+
 #define EVENT_TYPE_ZPASS_DONE                  0x15
 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT   0x16
 
@@ -1890,4 +1893,7 @@
 #define R_008970_VGT_NUM_INDICES                     0x008970
 #define R_0287F0_VGT_DRAW_INITIATOR                  0x0287F0
 
+#define R_03CFF0_SQ_VTX_BASE_VTX_LOC                    0x03CFF0
+#define R_03CFF4_SQ_VTX_START_INST_LOC                  0x03CFF4
+
 #endif
diff --git a/src/gallium/drivers/r600/r600_state.c 
b/src/gallium/drivers/r600/r600_state.c
index 83eedd2..c86bad7 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -126,6 +126,8 @@ static void r600_draw_common(struct r600_drawl *draw)
        r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, 
draw->max_index, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, 
draw->min_index, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, 
rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
+       r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 
0xFFFFFFFF, NULL);
+       r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 
0xFFFFFFFF, NULL);
        /* build late state */
        if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
                float offset_units = rctx->rasterizer->offset_units;
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 169cda5..02e3734 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -3489,6 +3489,9 @@
 #define R_028940_ALU_CONST_CACHE_PS_0                0x00028940
 #define R_028980_ALU_CONST_CACHE_VS_0                0x00028980
 
+#define R_03CFF0_SQ_VTX_BASE_VTX_LOC                 0x03CFF0
+#define R_03CFF4_SQ_VTX_START_INST_LOC               0x03CFF4
+
 #define SQ_TEX_INST_LD 0x03
 #define SQ_TEX_INST_GET_GRADIENTS_H 0x7
 #define SQ_TEX_INST_GET_GRADIENTS_V 0x8
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c 
b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index a92c32e..225027b 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -61,6 +61,11 @@ static const struct r600_reg evergreen_config_reg_list[] = {
        {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, 
R_00913C_SPI_CONFIG_CNTL_1, 0, 0},
 };
 
+static const struct r600_reg evergreen_ctl_const_list[] = {
+       {PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET, 
R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0},
+       {PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET, 
R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
+};
+
 static const struct r600_reg evergreen_context_reg_list[] = {
        {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, 
R_028000_DB_RENDER_CONTROL, 0, 0},
        {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, 
R_028004_DB_COUNT_CONTROL, 0, 0},
@@ -518,6 +523,11 @@ int evergreen_context_init(struct r600_context *ctx, 
struct radeon *radeon)
                                   Elements(evergreen_context_reg_list));
        if (r)
                goto out_err;
+       r = r600_context_add_block(ctx, evergreen_ctl_const_list,
+                                  Elements(evergreen_ctl_const_list));
+       if (r)
+               goto out_err;
+
 
        /* PS SAMPLER */
        for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c 
b/src/gallium/winsys/r600/drm/r600_hw_context.c
index 53783e8..88a86d2 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -134,6 +134,11 @@ static const struct r600_reg r600_config_reg_list[] = {
        {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009838_DB_WATERMARKS, 
0, 0},
 };
 
+static const struct r600_reg r600_ctl_const_list[] = {
+       {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, 
R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0},
+       {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, 
R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
+};
+
 static const struct r600_reg r600_context_reg_list[] = {
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, 
R_0286C8_SPI_THREAD_GROUPING, 0, 0},
@@ -591,6 +596,10 @@ int r600_context_init(struct r600_context *ctx, struct 
radeon *radeon)
                                   Elements(r600_context_reg_list));
        if (r)
                goto out_err;
+       r = r600_context_add_block(ctx, r600_ctl_const_list,
+                                  Elements(r600_ctl_const_list));
+       if (r)
+               goto out_err;
 
        /* PS SAMPLER BORDER */
        for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
diff --git a/src/gallium/winsys/r600/drm/r600d.h 
b/src/gallium/winsys/r600/drm/r600d.h
index 5c08c5a..ccc9ffa 100644
--- a/src/gallium/winsys/r600/drm/r600d.h
+++ b/src/gallium/winsys/r600/drm/r600d.h
@@ -2205,4 +2205,7 @@
 #define R_028940_ALU_CONST_CACHE_PS_0                0x00028940
 #define R_028980_ALU_CONST_CACHE_VS_0                0x00028980
 
+#define R_03CFF0_SQ_VTX_BASE_VTX_LOC                 0x03CFF0
+#define R_03CFF4_SQ_VTX_START_INST_LOC               0x03CFF4
+
 #endif

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