Module: Mesa Branch: master Commit: d22a1247d8a709cf433a6dd99b2f87a224c27d88 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d22a1247d8a709cf433a6dd99b2f87a224c27d88
Author: Jerome Glisse <[email protected]> Date: Mon Oct 4 10:25:23 2010 -0400 r600g: allow r600_bo to be a sub allocation of a big bo Add bo offset everywhere needed if r600_bo is ever a sub bo of a bigger bo. Signed-off-by: Jerome Glisse <[email protected]> --- src/gallium/drivers/r600/evergreen_state.c | 24 ++++++++++--------- src/gallium/drivers/r600/r600.h | 7 +++++- src/gallium/drivers/r600/r600_shader.c | 6 ++-- src/gallium/drivers/r600/r600_state.c | 20 +++++++++------- src/gallium/winsys/r600/drm/evergreen_hw_context.c | 2 +- src/gallium/winsys/r600/drm/r600_hw_context.c | 6 ++-- 6 files changed, 37 insertions(+), 28 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 6fcb2ae..06cdd5f 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -458,9 +458,9 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte S_030004_TEX_DEPTH(texture->depth0 - 1), 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2, - tmp->offset[0] >> 8, 0xFFFFFFFF, bo[0]); + (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]); r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3, - tmp->offset[1] >> 8, 0xFFFFFFFF, bo[1]); + (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]); r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4, word4 | S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) | S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) | @@ -765,7 +765,7 @@ static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state /* FIXME handle enabling of CB beyond BASE8 which has different offset */ r600_pipe_state_add_reg(rstate, R_028C60_CB_COLOR0_BASE + cb * 0x3C, - state->cbufs[cb]->offset >> 8, 0xFFFFFFFF, bo[0]); + (state->cbufs[cb]->offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]); r600_pipe_state_add_reg(rstate, R_028C78_CB_COLOR0_DIM + cb * 0x3C, 0x0, 0xFFFFFFFF, NULL); @@ -813,9 +813,9 @@ static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state format = r600_translate_dbformat(state->zsbuf->texture->format); r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE, - state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo); + (state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo); r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE, - state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo); + (state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo); // r600_pipe_state_add_reg(rstate, R_028014_DB_HTILE_DATA_BASE, state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo); r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, @@ -945,7 +945,7 @@ static void evergreen_set_constant_buffer(struct pipe_context *ctx, uint shader, 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(&rctx->vs_const_buffer, R_028980_ALU_CONST_CACHE_VS_0, - 0, 0xFFFFFFFF, rbuffer->bo); + (r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo); r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer); break; case PIPE_SHADER_FRAGMENT: @@ -956,7 +956,7 @@ static void evergreen_set_constant_buffer(struct pipe_context *ctx, uint shader, 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(&rctx->ps_const_buffer, R_028940_ALU_CONST_CACHE_PS_0, - 0, 0xFFFFFFFF, rbuffer->bo); + (r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo); r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer); break; default: @@ -1412,7 +1412,9 @@ void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info) j = rctx->vertex_elements->elements[i].vertex_buffer_index; vertex_buffer = &rctx->vertex_buffer[j]; rbuffer = (struct r600_resource*)vertex_buffer->buffer; - offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset; + offset = rctx->vertex_elements->elements[i].src_offset + + vertex_buffer->buffer_offset + + r600_bo_offset(rbuffer->bo); format = r600_translate_vertex_data_type(rctx->vertex_elements->elements[i].src_format); @@ -1567,7 +1569,7 @@ void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(rstate, R_028840_SQ_PGM_START_PS, - 0x00000000, 0xFFFFFFFF, shader->bo); + (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo); r600_pipe_state_add_reg(rstate, R_028844_SQ_PGM_RESOURCES_PS, S_028844_NUM_GPRS(rshader->bc.ngpr) | @@ -1640,10 +1642,10 @@ void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader 0x00000000, 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(rstate, R_02885C_SQ_PGM_START_VS, - 0x00000000, 0xFFFFFFFF, shader->bo); + (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo); r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS, - 0x00000000, 0xFFFFFFFF, shader->bo); + (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo); r600_pipe_state_add_reg(rstate, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF, diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h index dd3c4e3..8a2e5c5 100644 --- a/src/gallium/drivers/r600/r600.h +++ b/src/gallium/drivers/r600/r600.h @@ -102,7 +102,7 @@ enum chip_class { enum radeon_family r600_get_family(struct radeon *rw); enum chip_class r600_get_family_class(struct radeon *radeon); -/* lowlevel WS bo */ +/* r600_bo.c */ struct r600_bo; struct r600_bo *r600_bo(struct radeon *radeon, unsigned size, unsigned alignment, unsigned usage); @@ -112,6 +112,11 @@ void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, voi void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo); void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst, struct r600_bo *src); +static INLINE unsigned r600_bo_offset(struct r600_bo *bo) +{ + return 0; +} + /* R600/R700 STATES */ #define R600_GROUP_MAX 16 diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index e9d4ee1..d7edf6a 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -77,10 +77,10 @@ static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shade 0x00000000, 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(rstate, R_028858_SQ_PGM_START_VS, - 0x00000000, 0xFFFFFFFF, shader->bo); + r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo); r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS, - 0x00000000, 0xFFFFFFFF, shader->bo); + r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo); r600_pipe_state_add_reg(rstate, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF, @@ -167,7 +167,7 @@ static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shade r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(rstate, R_028840_SQ_PGM_START_PS, - 0x00000000, 0xFFFFFFFF, shader->bo); + r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo); r600_pipe_state_add_reg(rstate, R_028850_SQ_PGM_RESOURCES_PS, S_028868_NUM_GPRS(rshader->bc.ngpr) | diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 326e3aa..f7c77cd 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -94,7 +94,9 @@ static void r600_draw_common(struct r600_drawl *draw) j = rctx->vertex_elements->elements[i].vertex_buffer_index; vertex_buffer = &rctx->vertex_buffer[j]; rbuffer = (struct r600_resource*)vertex_buffer->buffer; - offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset; + offset = rctx->vertex_elements->elements[i].src_offset + + vertex_buffer->buffer_offset + + r600_bo_offset(rbuffer->bo); format = r600_translate_vertex_data_type(rctx->vertex_elements->elements[i].src_format); @@ -660,9 +662,9 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c S_038004_TEX_DEPTH(texture->depth0 - 1) | S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2, - tmp->offset[0] >> 8, 0xFFFFFFFF, bo[0]); + (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]); r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3, - tmp->offset[1] >> 8, 0xFFFFFFFF, bo[1]); + (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]); r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4, word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) | S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) | @@ -966,7 +968,7 @@ static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta r600_pipe_state_add_reg(rstate, R_028040_CB_COLOR0_BASE + cb * 4, - state->cbufs[cb]->offset >> 8, 0xFFFFFFFF, bo[0]); + (state->cbufs[cb]->offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]); r600_pipe_state_add_reg(rstate, R_0280A0_CB_COLOR0_INFO + cb * 4, color_info, 0xFFFFFFFF, bo[0]); @@ -980,10 +982,10 @@ static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta 0x00000000, 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(rstate, R_0280E0_CB_COLOR0_FRAG + cb * 4, - 0x00000000, 0xFFFFFFFF, bo[1]); + r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]); r600_pipe_state_add_reg(rstate, R_0280C0_CB_COLOR0_TILE + cb * 4, - 0x00000000, 0xFFFFFFFF, bo[2]); + r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]); r600_pipe_state_add_reg(rstate, R_028100_CB_COLOR0_MASK + cb * 4, 0x00000000, 0xFFFFFFFF, NULL); @@ -1013,7 +1015,7 @@ static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta format = r600_translate_dbformat(state->zsbuf->texture->format); r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE, - state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo); + (state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo); r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice), 0xFFFFFFFF, NULL); @@ -1157,7 +1159,7 @@ static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(&rctx->vs_const_buffer, R_028980_ALU_CONST_CACHE_VS_0, - 0, 0xFFFFFFFF, rbuffer->bo); + r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo); r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer); break; case PIPE_SHADER_FRAGMENT: @@ -1168,7 +1170,7 @@ static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(&rctx->ps_const_buffer, R_028940_ALU_CONST_CACHE_PS_0, - 0, 0xFFFFFFFF, rbuffer->bo); + r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo); r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer); break; default: diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c b/src/gallium/winsys/r600/drm/evergreen_hw_context.c index fadfe28..f51b14e 100644 --- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c +++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c @@ -817,7 +817,7 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances; if (draw->indices) { ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3); - ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset; + ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset + r600_bo_offset(draw->indices); ctx->pm4[ctx->pm4_cdwords++] = 0; ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices; ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator; diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c index 48727b9..61e3fbc 100644 --- a/src/gallium/winsys/r600/drm/r600_hw_context.c +++ b/src/gallium/winsys/r600/drm/r600_hw_context.c @@ -967,7 +967,7 @@ void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw) ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances; if (draw->indices) { ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3); - ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset; + ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset + r600_bo_offset(draw->indices); ctx->pm4[ctx->pm4_cdwords++] = 0; ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices; ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator; @@ -1180,7 +1180,7 @@ void r600_query_begin(struct r600_context *ctx, struct r600_query *query) /* emit begin query */ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2); ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_ZPASS_DONE; - ctx->pm4[ctx->pm4_cdwords++] = query->num_results; + ctx->pm4[ctx->pm4_cdwords++] = query->num_results + r600_bo_offset(query->buffer); ctx->pm4[ctx->pm4_cdwords++] = 0; ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); ctx->pm4[ctx->pm4_cdwords++] = 0; @@ -1196,7 +1196,7 @@ void r600_query_end(struct r600_context *ctx, struct r600_query *query) /* emit begin query */ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2); ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_ZPASS_DONE; - ctx->pm4[ctx->pm4_cdwords++] = query->num_results + 8; + ctx->pm4[ctx->pm4_cdwords++] = query->num_results + 8 + r600_bo_offset(query->buffer); ctx->pm4[ctx->pm4_cdwords++] = 0; ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); ctx->pm4[ctx->pm4_cdwords++] = 0; _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
