Module: Mesa Branch: master Commit: a112cc283d2c62f895cdd6aceb976b3c7ef5f59d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a112cc283d2c62f895cdd6aceb976b3c7ef5f59d
Author: Dave Airlie <[email protected]> Date: Tue Feb 1 14:22:08 2011 +1000 r600g: align the tiling modes with what the DDX and kernel expects. If we see a MACRO bit on r600g its 2D tiled, if don't see a MACRO bit and we do see a MICRO bit then its 1D tiled. Signed-off-by: Dave Airlie <[email protected]> --- src/gallium/winsys/r600/drm/r600_bo.c | 7 +++---- 1 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/gallium/winsys/r600/drm/r600_bo.c b/src/gallium/winsys/r600/drm/r600_bo.c index 6a3737f..edd774e 100644 --- a/src/gallium/winsys/r600/drm/r600_bo.c +++ b/src/gallium/winsys/r600/drm/r600_bo.c @@ -95,11 +95,10 @@ struct r600_bo *r600_bo_handle(struct radeon *radeon, radeon_bo_get_tiling_flags(radeon, rbo, &bo->tiling_flags, &bo->kernel_pitch); if (array_mode) { if (bo->tiling_flags) { - if (bo->tiling_flags & RADEON_TILING_MICRO) - *array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; - if ((bo->tiling_flags & (RADEON_TILING_MICRO | RADEON_TILING_MACRO)) == - (RADEON_TILING_MICRO | RADEON_TILING_MACRO)) + if (bo->tiling_flags & RADEON_TILING_MACRO) *array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; + else if (bo->tiling_flags & RADEON_TILING_MICRO) + *array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; } else { *array_mode = 0; } _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
