Module: Mesa Branch: master Commit: 667cdba2118cf82e0027bf44314c9d1334d00840 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=667cdba2118cf82e0027bf44314c9d1334d00840
Author: Tom Stellard <[email protected]> Date: Fri May 25 10:59:52 2012 -0400 radeon/llvm: Use a custom inserter to lower FNEG --- src/gallium/drivers/radeon/AMDGPUInstructions.td | 7 +++++++ src/gallium/drivers/radeon/AMDILInstructions.td | 5 ----- src/gallium/drivers/radeon/R600ISelLowering.cpp | 7 +++++++ src/gallium/drivers/radeon/R600Instructions.td | 1 + .../drivers/radeon/R600LowerInstructions.cpp | 17 ----------------- 5 files changed, 15 insertions(+), 22 deletions(-) diff --git a/src/gallium/drivers/radeon/AMDGPUInstructions.td b/src/gallium/drivers/radeon/AMDGPUInstructions.td index 1f0d582..a004b9c 100644 --- a/src/gallium/drivers/radeon/AMDGPUInstructions.td +++ b/src/gallium/drivers/radeon/AMDGPUInstructions.td @@ -74,6 +74,13 @@ class FABS <RegisterClass rc> : AMDGPUShaderInst < [(set rc:$dst, (fabs rc:$src0))] >; +class FNEG <RegisterClass rc> : AMDGPUShaderInst < + (outs rc:$dst), + (ins rc:$src0), + "FNEG $dst, $src0", + [(set rc:$dst, (fneg rc:$src0))] +>; + } // End isPseudo = 1, hasCustomInserter = 1 } // End isCodeGenOnly = 1 diff --git a/src/gallium/drivers/radeon/AMDILInstructions.td b/src/gallium/drivers/radeon/AMDILInstructions.td index 869c2bb..0197e94 100644 --- a/src/gallium/drivers/radeon/AMDILInstructions.td +++ b/src/gallium/drivers/radeon/AMDILInstructions.td @@ -50,7 +50,6 @@ def INTTOANY_i16: OneInOneOut<IL_OP_MOV, (outs GPRI16:$dst), (ins GPRI32:$src0), //===---------------------------------------------------------------------===// // Signed 32bit integer math instructions start here //===---------------------------------------------------------------------===// -defm NEGATE : UnaryOpMCi32<IL_OP_I_NEGATE, IL_inegate>; // get rid of the addri via the tablegen instead of custom lowered instruction defm EADD : BinaryOpMCi32<IL_OP_I_ADD, adde>; def INTTOANY_i32: OneInOneOut<IL_OP_MOV, (outs GPRI32:$dst), (ins GPRI32:$src0), @@ -238,10 +237,6 @@ defm NEAR : UnaryOpMCf32<IL_OP_ROUND_NEAR, fnearbyint>; defm RND_Z : UnaryOpMCf32<IL_OP_ROUND_ZERO, ftrunc>; // This opcode has custom swizzle pattern encoded in Swizzle Encoder -def NEG_f32 : OneInOneOut<IL_OP_MOV, (outs GPRF32:$dst), - (ins GPRF32:$src0), - !strconcat(IL_OP_MOV.Text, " $dst, $src0"), - [(set GPRF32:$dst, (fneg GPRF32:$src0))]>; def INTTOANY_f32 : OneInOneOut<IL_OP_MOV, (outs GPRF32:$dst), (ins GPRI32:$src0), !strconcat(IL_OP_MOV.Text, " $dst, $src0"), diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp index 59a2bb1..de60a2d 100644 --- a/src/gallium/drivers/radeon/R600ISelLowering.cpp +++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp @@ -115,6 +115,13 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( .addOperand(MI->getOperand(1)); break; + case AMDIL::FNEG_R600: + MI->getOperand(1).addTargetFlag(MO_FLAG_NEG); + BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDIL::MOV)) + .addOperand(MI->getOperand(0)) + .addOperand(MI->getOperand(1)); + break; + case AMDIL::R600_LOAD_CONST: { int64_t RegIndex = MI->getOperand(1).getImm(); diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td index 22f3fc1..a2a509e 100644 --- a/src/gallium/drivers/radeon/R600Instructions.td +++ b/src/gallium/drivers/radeon/R600Instructions.td @@ -1070,6 +1070,7 @@ def TXD_SHADOW: AMDGPUShaderInst < def CLAMP_R600 : CLAMP <R600_Reg32>; def FABS_R600 : FABS<R600_Reg32>; +def FNEG_R600 : FNEG<R600_Reg32>; let isPseudo = 1 in { diff --git a/src/gallium/drivers/radeon/R600LowerInstructions.cpp b/src/gallium/drivers/radeon/R600LowerInstructions.cpp index 1795b38..3b96b19 100644 --- a/src/gallium/drivers/radeon/R600LowerInstructions.cpp +++ b/src/gallium/drivers/radeon/R600LowerInstructions.cpp @@ -224,23 +224,6 @@ bool R600LowerInstructionsPass::runOnMachineFunction(MachineFunction &MF) continue; } - case AMDIL::NEGATE_i32: - BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::SUB_INT)) - .addOperand(MI.getOperand(0)) - .addReg(AMDIL::ZERO) - .addOperand(MI.getOperand(1)); - break; - - case AMDIL::NEG_f32: - { - MI.getOperand(1).addTargetFlag(MO_FLAG_NEG); - BuildMI(MBB, I, MBB.findDebugLoc(I), - TII->get(TII->getISAOpcode(AMDIL::MOV))) - .addOperand(MI.getOperand(0)) - .addOperand(MI.getOperand(1)); - break; - } - case AMDIL::ULT: BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::SETGT_UINT)) .addOperand(MI.getOperand(0)) _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
