Module: Mesa
Branch: master
Commit: a460df9299dfeb7915689befc15155e18e41ddb8
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a460df9299dfeb7915689befc15155e18e41ddb8

Author: Marek Olšák <[email protected]>
Date:   Sun Jul  8 00:23:41 2012 +0200

r600g: add assertions after translate_colorswap/colorformat/dbformat/texformat

---

 src/gallium/drivers/r600/evergreen_state.c |    9 ++++++++-
 src/gallium/drivers/r600/r600_state.c      |   11 +++++++++--
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 1572798..939e05b 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -983,8 +983,10 @@ static struct pipe_sampler_view 
*evergreen_create_sampler_view(struct pipe_conte
        format = r600_translate_texformat(ctx->screen, state->format,
                                          swizzle,
                                          &word4, &yuv_format);
+       assert(format != ~0);
        if (format == ~0) {
-               format = 0;
+               FREE(view);
+               return NULL;
        }
 
        if (tmp->is_depth && !tmp->is_flushing_texture) {
@@ -1415,7 +1417,11 @@ static void evergreen_cb(struct r600_context *rctx, 
struct r600_pipe_state *rsta
        }
 
        format = r600_translate_colorformat(surf->base.format);
+       assert(format != ~0);
+
        swap = r600_translate_colorswap(surf->base.format);
+       assert(swap != ~0);
+
        if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
                endian = ENDIAN_NONE;
        } else {
@@ -1534,6 +1540,7 @@ static void evergreen_db(struct r600_context *rctx, 
struct r600_pipe_state *rsta
        rtex = (struct r600_resource_texture*)surf->base.texture;
        first_layer = surf->base.u.tex.first_layer;
        format = r600_translate_dbformat(surf->base.format);
+       assert(format != ~0);
 
        offset = r600_resource_va(rctx->context.screen, surf->base.texture);
        /* XXX remove this once tiling is properly supported */
diff --git a/src/gallium/drivers/r600/r600_state.c 
b/src/gallium/drivers/r600/r600_state.c
index 3fd77da..d51c64b 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -995,8 +995,10 @@ static struct pipe_sampler_view 
*r600_create_sampler_view(struct pipe_context *c
        format = r600_translate_texformat(ctx->screen, state->format,
                                          swizzle,
                                          &word4, &yuv_format);
+       assert(format != ~0);
        if (format == ~0) {
-               format = 0;
+               FREE(view);
+               return NULL;
        }
 
        if (tmp->is_depth && !tmp->is_flushing_texture) {
@@ -1456,8 +1458,12 @@ static void r600_cb(struct r600_context *rctx, struct 
r600_pipe_state *rstate,
        }
 
        format = r600_translate_colorformat(surf->base.format);
+       assert(format != ~0);
+
        swap = r600_translate_colorswap(surf->base.format);
-       if(rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
+       assert(swap != ~0);
+
+       if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
                endian = ENDIAN_NONE;
        } else {
                endian = r600_colorformat_endian_swap(format);
@@ -1612,6 +1618,7 @@ static void r600_db(struct r600_context *rctx, struct 
r600_pipe_state *rstate,
        }
 
        format = r600_translate_dbformat(state->zsbuf->format);
+       assert(format != ~0);
 
        r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE,
                                offset >> 8, &rtex->resource, 
RADEON_USAGE_READWRITE);

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