Module: Mesa
Branch: master
Commit: 082874e3891e588f674508be6578f600b35852c4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=082874e3891e588f674508be6578f600b35852c4
Author: Paul Berry <stereotype...@gmail.com>
Date: Tue Jul 17 21:06:01 2012 -0700
i965/blorp: Properly adjust primitive size for 8x MSAA.
When rendering to an IMS MSAA surface on Gen7, blorp sets up the
rendering pipeline as though it were rendering to a single-sampled
surface; accordingly it must adjust the size of the primitive it sends
down the pipeline to account for the interleaving of samples in an IMS
surface.
This patch modifies the size adjustment code to properly handle 8x
MSAA, which makes room for the extra samples by using an interleaving
pattern that is twice as wide as 4x MSAA.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 21 +++++++++++++++++----
1 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index ae60ae2..f77008d 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1633,10 +1633,23 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
* pipeline as multisampled.
*/
assert(dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS);
- x0 = (x0 * 2) & ~3;
- y0 = (y0 * 2) & ~3;
- x1 = ALIGN(x1 * 2, 4);
- y1 = ALIGN(y1 * 2, 4);
+ switch (dst_mt->num_samples) {
+ case 4:
+ x0 = (x0 * 2) & ~3;
+ y0 = (y0 * 2) & ~3;
+ x1 = ALIGN(x1 * 2, 4);
+ y1 = ALIGN(y1 * 2, 4);
+ break;
+ case 8:
+ x0 = (x0 * 4) & ~7;
+ y0 = (y0 * 2) & ~3;
+ x1 = ALIGN(x1 * 4, 8);
+ y1 = ALIGN(y1 * 2, 4);
+ break;
+ default:
+ assert(!"Unrecognized sample count in brw_blorp_blit_params ctor");
+ break;
+ }
wm_prog_key.use_kill = true;
}
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