Module: Mesa Branch: master Commit: 1f112ccf02adaf35317a356f40a71b16de637f97 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f112ccf02adaf35317a356f40a71b16de637f97
Author: Eric Anholt <[email protected]> Date: Mon Mar 18 15:38:58 2013 -0700 i965/gen7: Align all depth miplevels to 8 in the X direction. On an INTEL_DEBUG=perf piglit run on IVB, reduces the instances of "HW workaround: blit" (the printouts from the misaligned-depth workaround blits) from 725 to 675. It doesn't totally eliminate the workaround blit, because we still have problems with Y offsets that we can't fix (since texturing can only align miplevels up to 2 or 4, not 8). No regressions on piglit/es3conform on IVB. Reviewed-by: Kenneth Graunke <[email protected]> --- src/mesa/drivers/dri/intel/intel_tex_layout.c | 10 +++++++++- 1 files changed, 9 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.c b/src/mesa/drivers/dri/intel/intel_tex_layout.c index 35030df..59d4bc3 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_layout.c +++ b/src/mesa/drivers/dri/intel/intel_tex_layout.c @@ -77,7 +77,15 @@ intel_horizontal_texture_alignment_unit(struct intel_context *intel, if (format == MESA_FORMAT_S8) return 8; - if (intel->gen >= 7 && format == MESA_FORMAT_Z16) + /* The depth alignment requirements in the table above are for rendering to + * depth miplevels using the LOD control fields. We don't use LOD control + * fields, and instead use page offsets plus intra-tile x/y offsets, which + * require that the low 3 bits are zero. To reduce the number of x/y + * offset workaround blits we do, align the X to 8, which depth texturing + * can handle (sadly, it can't handle 8 in the Y direction). + */ + if (intel->gen >= 7 && + _mesa_get_format_base_format(format) == GL_DEPTH_COMPONENT) return 8; return 4; _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
