Module: Mesa Branch: master Commit: 55ecc448b9d05e9f1e5ceb88ab35606e80e3adee URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=55ecc448b9d05e9f1e5ceb88ab35606e80e3adee
Author: Kenneth Graunke <[email protected]> Date: Mon Apr 8 19:27:38 2013 -0700 i965: Prefer Y-tiling on Gen6+. In the past, we preferred X-tiling for color buffers because our BLT code couldn't handle Y-tiling. However, the BLT paths have been largely replaced by BLORP on Gen6+, which can handle any kind of tiling. We hadn't measured any performance improvement in the past, but that's probably because compressed textures were all untiled anyway. Improves performance in GLB27_TRex_C24Z16_FixedTime by 7.69231%. v2: Rebase on top of Eric's untiled-for-larger-than-aperture changes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]> --- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index 859bcd6..38c0149 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -346,7 +346,7 @@ intel_miptree_choose_tiling(struct intel_context *intel, if (width0 >= 64) { if (ALIGN(mt->total_width * mt->cpp, 512) < 32768) - return I915_TILING_X; + return intel->gen >= 6 ? I915_TILING_Y : I915_TILING_X; perf_debug("%dx%d miptree too large to blit, falling back to untiled", mt->total_width, mt->total_height); _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
