Module: Mesa Branch: master Commit: 1d09a8c3cdf02ed2c17f263d120d45e96562a5e1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d09a8c3cdf02ed2c17f263d120d45e96562a5e1
Author: Matt Turner <[email protected]> Date: Thu Apr 11 15:49:32 2013 -0700 i965: Lower bitfieldInsert. v2: Only lower bitfieldInsert to BFM+BFI (and don't lower bitfieldExtract at all) since three-source instructions are now usable in the vertex shader. v3: Lower bitfield_insert in the same pass with everything else, since it doesn't produce any instructions to be lowered (the other two lowering passes that were in a previous iteration of this series emitted subtractions which needed to be lowered). Reviewed-by: Chris Forbes <[email protected]> [v2] --- src/mesa/drivers/dri/i965/brw_shader.cpp | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 3c63ba3..3bbcccd 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -152,6 +152,9 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) */ brw_lower_packing_builtins(brw, (gl_shader_type) stage, shader->ir); do_mat_op_to_vec(shader->ir); + const int bitfield_insert = intel->gen >= 7 + ? BITFIELD_INSERT_TO_BFM_BFI + : 0; const int lrp_to_arith = intel->gen < 6 ? LRP_TO_ARITH : 0; lower_instructions(shader->ir, MOD_TO_FRACT | @@ -159,6 +162,7 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) SUB_TO_ADD_NEG | EXP_TO_EXP2 | LOG_TO_LOG2 | + bitfield_insert | lrp_to_arith); /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this, _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
