Module: Mesa Branch: master Commit: e6893b99adcd6d9fb1bd49067883f66cc5603fe7 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6893b99adcd6d9fb1bd49067883f66cc5603fe7
Author: Ville Syrjälä <[email protected]> Date: Mon Aug 12 16:07:08 2013 +0300 i965/gen7: Set MOCS L3 cacheability for IVB/BYT (v2) IVB/BYT also has the same L3 cacheability control in MOCS as HSW, so let's make use of it. pts/xonotic and pts/reaction @ 1920x1080 gain ~4% on my IVB GT2. Most other things show less gains/no regressions, except furmark which loses some 10 points. I didn't have a BYT at hand for testing. v2: Don't check (brw->gen == 7) in gen7 functions. (chadv) Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Chad Versace <[email protected]> --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 2 +- src/mesa/drivers/dri/i965/brw_misc_state.c | 2 +- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 4 ++-- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 6 +++--- src/mesa/drivers/dri/i965/gen7_misc_state.c | 2 +- src/mesa/drivers/dri/i965/gen7_vs_state.c | 4 +--- src/mesa/drivers/dri/i965/gen7_wm_state.c | 4 +--- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 5 ++--- 8 files changed, 12 insertions(+), 17 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 158c9e5..390b4a3 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -659,7 +659,7 @@ static void brw_emit_vertices(struct brw_context *brw) if (brw->gen >= 7) dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE; - if (brw->is_haswell) + if (brw->gen == 7) dw0 |= GEN7_MOCS_L3 << 16; OUT_BATCH(dw0 | (buffer->stride << BRW_VB0_PITCH_SHIFT)); diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index f24fdaf..ac7f1f4 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -1038,7 +1038,7 @@ static void upload_state_base_address( struct brw_context *brw ) */ if (brw->gen >= 6) { - uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; + uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0; if (brw->gen == 6) intel_emit_post_sync_nonzero_flush(brw); diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index b47466a..1c85921 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -74,7 +74,7 @@ void gen6_blorp_emit_state_base_address(struct brw_context *brw, const brw_blorp_params *params) { - uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; + uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0; BEGIN_BATCH(10); OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2)); @@ -168,7 +168,7 @@ gen6_blorp_emit_vertices(struct brw_context *brw, if (brw->gen >= 7) dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE; - if (brw->is_haswell) + if (brw->gen == 7) dw0 |= GEN7_MOCS_L3 << 16; BEGIN_BATCH(batch_length); diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 44e7578..a387836 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -143,7 +143,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw, */ struct intel_region *region = surface->mt->region; uint32_t tile_x, tile_y; - uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; + const uint8_t mocs = GEN7_MOCS_L3; uint32_t tiling = surface->map_stencil_as_y_tiled ? I915_TILING_Y : region->tiling; @@ -616,7 +616,7 @@ gen7_blorp_emit_constant_ps(struct brw_context *brw, const brw_blorp_params *params, uint32_t wm_push_const_offset) { - uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; + const uint8_t mocs = GEN7_MOCS_L3; /* Make sure the push constants fill an exact integer number of * registers. @@ -658,7 +658,7 @@ static void gen7_blorp_emit_depth_stencil_config(struct brw_context *brw, const brw_blorp_params *params) { - uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; + const uint8_t mocs = GEN7_MOCS_L3; uint32_t surfwidth, surfheight; uint32_t surftype; unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1); diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c index 51067b3..eb942cf 100644 --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c @@ -41,7 +41,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw, uint32_t tile_x, uint32_t tile_y) { struct gl_context *ctx = &brw->ctx; - uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; + const uint8_t mocs = GEN7_MOCS_L3; struct gl_framebuffer *fb = ctx->DrawBuffer; uint32_t surftype; unsigned int depth = 1; diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c index 7a6ba59..64a19fa 100644 --- a/src/mesa/drivers/dri/i965/gen7_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c @@ -63,8 +63,6 @@ upload_vs_state(struct brw_context *brw) OUT_BATCH(0); ADVANCE_BATCH(); } else { - uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; - BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2)); OUT_BATCH(brw->vs.push_const_size); @@ -72,7 +70,7 @@ upload_vs_state(struct brw_context *brw) /* Pointer to the VS constant buffer. Covered by the set of * state flags from gen6_prepare_wm_contants */ - OUT_BATCH(brw->vs.push_const_offset | mocs); + OUT_BATCH(brw->vs.push_const_offset | GEN7_MOCS_L3); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index ba7a53d..e88db78 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -141,8 +141,6 @@ upload_ps_state(struct brw_context *brw) OUT_BATCH(0); ADVANCE_BATCH(); } else { - uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; - BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2)); @@ -152,7 +150,7 @@ upload_ps_state(struct brw_context *brw) /* Pointer to the WM constant buffer. Covered by the set of * state flags from gen6_upload_wm_push_constants. */ - OUT_BATCH(brw->wm.push_const_offset | mocs); + OUT_BATCH(brw->wm.push_const_offset | GEN7_MOCS_L3); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index cdd2242..91f854b 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -286,7 +286,6 @@ gen7_update_texture_surface(struct gl_context *ctx, struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel]; struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit); uint32_t tile_x, tile_y; - uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; if (tObj->Target == GL_TEXTURE_BUFFER) { gen7_update_buffer_texture_surface(ctx, unit, binding_table, surf_index); @@ -335,7 +334,7 @@ gen7_update_texture_surface(struct gl_context *ctx, */ surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT | (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT | - SET_FIELD(mocs, GEN7_SURFACE_MOCS) | + SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) | /* mip count */ (intelObj->_MaxLevel - tObj->BaseLevel)); @@ -514,7 +513,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, bool is_array = false; int depth = MAX2(rb->Depth, 1); int min_array_element; - uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; + const uint8_t mocs = GEN7_MOCS_L3; GLenum gl_target = rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D; _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
