Module: Mesa Branch: master Commit: 3aef1fefb4dc2a66101725f2fdc3f2bb0eb926c2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3aef1fefb4dc2a66101725f2fdc3f2bb0eb926c2
Author: Kenneth Graunke <[email protected]> Date: Thu Oct 24 00:36:42 2013 -0700 i965: Emit post-sync non-zero flush before 3DSTATE_DRAWING_RECTANGLE. This is another non-pipelined command that needs a flush on Sandybridge. Signed-off-by: Kenneth Graunke <[email protected]> Tested-by: Xinkai Chen <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Cc: "9.2" <[email protected]> --- src/mesa/drivers/dri/i965/brw_misc_state.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 5d1c27d..70b0dbd 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -48,6 +48,10 @@ static void upload_drawing_rect(struct brw_context *brw) { struct gl_context *ctx = &brw->ctx; + /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined. */ + if (brw->gen == 6) + intel_emit_post_sync_nonzero_flush(brw); + BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2)); OUT_BATCH(0); /* xmin, ymin */ _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
