Module: Mesa Branch: 9.2 Commit: b60eb2e17446d0d581963d129ae6fcd98a9cb97f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b60eb2e17446d0d581963d129ae6fcd98a9cb97f
Author: Chad Versace <[email protected]> Date: Tue Nov 26 17:04:24 2013 -0800 i965/hsw: Apply non-msrt fast color clear w/a to all HSW GTs Pre-patch, the workaround was applied to only HSW GT3. However, the workaround also fixes render corruption on the HSW GT1 Chromebook, codenamed Falco. Also, update the BSpec quote that discusses the workaround to reflect the latest BSpec. The BSpec states that the workaround is required for Ivybridge and Baytrail as well as Haswell. But, we apply the workaround to only Haswell because (a) we suspect that is the only hardware where it is actually required and (b) we haven't yet validated the workaround for the other hardware. CC: "9.2, 10.0" <[email protected]> CC: Anuj Phogat <[email protected]> OTC-Tracker: CHRMOS-812 Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]> (cherry picked from commit 8b659cef3a244b1acdbbca0beb704a66b6bc2fbc) --- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 18 ++++++++++++------ 1 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp index f26f39d..7fe998a 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp @@ -261,13 +261,19 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct brw_context *brw, x_align *= 16; y_align *= 32; - if (brw->is_haswell && brw->gt == 3) { + if (brw->is_haswell) { /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel - * Backend > MCS Buffer for Render Target(s) [DevIVB+]: - * [DevHSW:GT3]: Clear rectangle must be aligned to two times the - * number of pixels in the table shown below... - * x_align, y_align values computed above are the relevant entries - * in the referred table. + * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color + * Clear of Non-MultiSampled Render Target Restrictions": + * + * [IVB, VLVT, HSW]: Clear rectangle must be aligned to two times + * the number of pixels in the table shown below... x_align, + * y_align values computed above are the relevant entries in the + * referred table. + * + * We apply the workaround to only Haswell because (a) we suspect that + * is the only hardware where it is actually required and (b) we + * haven't yet validated the workaround for the other hardware. */ x0 = ROUND_DOWN_TO(x0, 2 * x_align); y0 = ROUND_DOWN_TO(y0, 2 * y_align); _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
