Module: Mesa Branch: master Commit: e2198422820fd076adccde2f72b821a2c05e8fcc URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2198422820fd076adccde2f72b821a2c05e8fcc
Author: Marek Olšák <[email protected]> Date: Sun Mar 9 20:05:54 2014 +0100 radeonsi: set correct alignment for texture buffers and constant buffers I think these are all equivalent to vertex buffer fetches which should be dword-aligned. Scalar loads are also dword-aligned. Reviewed-by: Michel Dänzer <[email protected]> --- src/gallium/drivers/radeonsi/si_pipe.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 0efd4eb..0850269 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -265,13 +265,12 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param) return 64; case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: - return 256; + case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: + return 4; case PIPE_CAP_GLSL_FEATURE_LEVEL: return HAVE_LLVM >= 0x0305 ? 330 : 140; - case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: - return 1; case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF); _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
