Module: Mesa Branch: master Commit: c99f09f4be29f3f7560607edf001497e1b5abfbf URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c99f09f4be29f3f7560607edf001497e1b5abfbf
Author: Rob Clark <[email protected]> Date: Sat Aug 30 15:17:49 2014 -0400 freedreno/ir3: add TXB Signed-off-by: Rob Clark <[email protected]> --- src/gallium/drivers/freedreno/ir3/ir3_compiler.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c index b587ee0..371ab54 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c @@ -1123,6 +1123,7 @@ get_tex_info(struct ir3_compile_context *ctx, switch (inst->Instruction.Opcode) { case TGSI_OPCODE_TEX: + case TGSI_OPCODE_TXB: switch (tex) { case TGSI_TEXTURE_1D: return &tex1d; @@ -1259,6 +1260,9 @@ trans_samp(const struct instr_translater *t, add_dst_reg_wrmask(ctx, instr, dst, 0, dst->WriteMask); add_src_reg_wrmask(ctx, instr, coord, coord->SwizzleX, tinf->src_wrmask); + + if (t->tgsi_opc == TGSI_OPCODE_TXB) + add_src_reg_wrmask(ctx, instr, coord, coord->SwizzleW, 0x1); } /* @@ -2005,6 +2009,7 @@ static const struct instr_translater translaters[TGSI_OPCODE_LAST] = { INSTR(SIN, instr_cat4, .opc = OPC_SIN), INSTR(TEX, trans_samp, .opc = OPC_SAM, .arg = TGSI_OPCODE_TEX), INSTR(TXP, trans_samp, .opc = OPC_SAM, .arg = TGSI_OPCODE_TXP), + INSTR(TXB, trans_samp, .opc = OPC_SAMB, .arg = TGSI_OPCODE_TXB), INSTR(SGT, trans_cmp), INSTR(SLT, trans_cmp), INSTR(FSLT, trans_cmp), _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
