Module: Mesa Branch: master Commit: 51e335742e55d6725fd5c4558158769a32f70f22 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=51e335742e55d6725fd5c4558158769a32f70f22
Author: Rob Clark <[email protected]> Date: Sat Feb 21 13:55:37 2015 -0500 freedreno/a4xx: set PC_PRIM_VTX_CNTL.VAROUT properly Fixes xonotic, some webgl stuff, and really pretty much anything with more than 4 varyings. Signed-off-by: Rob Clark <[email protected]> --- src/gallium/drivers/freedreno/a4xx/fd4_emit.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c index 7359639..0e00e38 100644 --- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c +++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c @@ -440,7 +440,12 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring, ->pc_prim_vtx_cntl; val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE); - val |= COND(fp->total_in > 0, A4XX_PC_PRIM_VTX_CNTL_VAROUT(1)); + if (fp->total_in > 0) { + uint32_t varout = align(fp->total_in, 16) / 16; + if (varout > 1) + varout = align(varout, 2); + val |= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout); + } OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2); OUT_RING(ring, val); _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
