Module: Mesa Branch: master Commit: f5b37fb1acad9cf044b7b6d4fa5f2582bd8bc7f4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5b37fb1acad9cf044b7b6d4fa5f2582bd8bc7f4
Author: Francisco Jerez <[email protected]> Date: Wed Aug 5 16:43:37 2015 +0300 i965/fs: Lower 32x32 bit multiplication on BXT. AFAIK BXT has the same annoying alignment limitation as CHV on the source register regions of 32x32 bit MULs, give it the same treatment. Reviewed-by: Matt Turner <[email protected]> --- src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 15fe364..0278237 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -3130,9 +3130,9 @@ fs_visitor::lower_integer_multiplication() bool progress = false; /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit operation - * directly, but Cherryview cannot. + * directly, but CHV/BXT cannot. */ - if (devinfo->gen >= 8 && !devinfo->is_cherryview) + if (devinfo->gen >= 8 && !devinfo->is_cherryview && !devinfo->is_broxton) return false; foreach_block_and_inst_safe(block, fs_inst, inst, cfg) { _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
