Module: Mesa
Branch: master
Commit: 8168dfdd4e63457bd8a9ef04a5d49a1f2e202ab8
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8168dfdd4e63457bd8a9ef04a5d49a1f2e202ab8

Author: Dave Airlie <[email protected]>
Date:   Wed Feb 18 23:51:19 2015 +0000

r600: geometry shader gsvs itemsize workaround

On some chips the GSVS itemsize needs to be aligned to a cacheline size.

This only applies to some of the r600 family chips.

Reviewed-by: Marek Olšák <[email protected]>
Cc: "10.6 11.0 11.1" <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>

---

 src/gallium/drivers/r600/r600_state.c |   20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/src/gallium/drivers/r600/r600_state.c 
b/src/gallium/drivers/r600/r600_state.c
index c2d4abc..c59e6c0 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -2675,6 +2675,9 @@ void r600_update_vs_state(struct pipe_context *ctx, 
struct r600_pipe_shader *sha
                S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
 }
 
+#define RV610_GSVS_ALIGN 32
+#define R600_GSVS_ALIGN 16
+
 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader 
*shader)
 {
        struct r600_context *rctx = (struct r600_context *)ctx;
@@ -2684,6 +2687,23 @@ void r600_update_gs_state(struct pipe_context *ctx, 
struct r600_pipe_shader *sha
        unsigned gsvs_itemsize =
                        (cp_shader->ring_item_sizes[0] * 
shader->selector->gs_max_out_vertices) >> 2;
 
+       /* some r600s needs gsvs itemsize aligned to cacheline size
+          this was fixed in rs780 and above. */
+       switch (rctx->b.family) {
+       case CHIP_RV610:
+               gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN);
+               break;
+       case CHIP_R600:
+       case CHIP_RV630:
+       case CHIP_RV670:
+       case CHIP_RV620:
+       case CHIP_RV635:
+               gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN);
+               break;
+       default:
+               break;
+       }
+
        r600_init_command_buffer(cb, 64);
 
        /* VGT_GS_MODE is written by r600_emit_shader_stages */

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