Module: Mesa Branch: master Commit: 4ebcf5194d98b47bd9e8a72b7418054708b14750 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ebcf5194d98b47bd9e8a72b7418054708b14750
Author: Dave Airlie <[email protected]> Date: Tue Feb 24 15:58:33 2015 +1000 r600: increment ring index after emit vertex not before. The docs say we should send the emit after the ring writes, so lets do that and not have an ALU in between. Signed-off-by: Dave Airlie <[email protected]> --- src/gallium/drivers/r600/r600_shader.c | 42 ++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 18 deletions(-) diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index fe4a27d..e258d76 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -1793,6 +1793,27 @@ static int generate_gs_copy_shader(struct r600_context *rctx, return r600_bytecode_build(ctx.bc); } +static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind) +{ + if (ind) { + struct r600_bytecode_alu alu; + int r; + + memset(&alu, 0, sizeof(struct r600_bytecode_alu)); + alu.op = ALU_OP2_ADD_INT; + alu.src[0].sel = ctx->gs_export_gpr_tregs[idx]; + alu.src[1].sel = V_SQ_ALU_SRC_LITERAL; + alu.src[1].value = ctx->gs_out_ring_offset >> 4; + alu.dst.sel = ctx->gs_export_gpr_tregs[idx]; + alu.dst.write = 1; + alu.last = 1; + r = r600_bytecode_add_alu(ctx->bc, &alu); + if (r) + return r; + } + return 0; +} + static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind) { struct r600_bytecode_output output; @@ -1859,23 +1880,6 @@ static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_st r600_bytecode_add_output(ctx->bc, &output); } - if (ind) { - /* get a temp and add the ring offset to the next vertex base in the shader */ - struct r600_bytecode_alu alu; - int r; - - memset(&alu, 0, sizeof(struct r600_bytecode_alu)); - alu.op = ALU_OP2_ADD_INT; - alu.src[0].sel = ctx->gs_export_gpr_tregs[effective_stream]; - alu.src[1].sel = V_SQ_ALU_SRC_LITERAL; - alu.src[1].value = ctx->gs_out_ring_offset >> 4; - alu.dst.sel = ctx->gs_export_gpr_tregs[effective_stream]; - alu.dst.write = 1; - alu.last = 1; - r = r600_bytecode_add_alu(ctx->bc, &alu); - if (r) - return r; - } ++ctx->gs_next_vertex; return 0; } @@ -7772,8 +7776,10 @@ static int tgsi_gs_emit(struct r600_shader_ctx *ctx) emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE); r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op); - if (!r) + if (!r) { ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream + return emit_inc_ring_offset(ctx, stream, TRUE); + } return r; } _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
